Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fill. - Akihiro Horibe; Fumiaki Yamada (3DIC, 2009)

High density 3D integration by pre-applied Inter Chip Fill. - Akihiro Horibe; Kuniaki Sueoka; Katsuyuki Sakuma; Sayuri Kohara; Keiji Matsumoto; Hidekazu Kikuchi; Yasumitsu Orii; Toshiro Mitsuhashi; Fumiaki Yamada (3DIC, 2010)

Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration. - Sayuri Kohara; Akihiro Horibe; Kuniaki Sueoka; Keiji Matsumoto; Fumiaki Yamada; Yasumitsu Orii; Katsuyuki Sakuma; Takahiro Kinoshita; Takashi Kawakami (3DIC, 2011)

Thermo-mechanical evaluation of 3D packages. - Sayuri Kohara; Akihiro Horibe; Kuniaki Sueoka; Keiji Matsumoto; Fumiaki Yamada; Hiroyuki Mori; Yasumitsu Orii (3DIC, 2013)

Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration. - Kuniaki Sueoka; Akihiro Horibe; T. Aoki; Sayuri Kohara; Kazushige Toriyama; Hiroyuki Mori; Yasumitsu Orii (3DIC, 2015)

Photonic Modules with High Density Polymer Waveguide Interface. - Jean Benoit Héroux; A. Paz Ramos; F. Arguin; Yan Thibodeau; B. Terjani; Hidetoshi Numata; C. Marushima; Sayuri Kohara; Akihiro Horibe; H. Mori; Y. Taira; H. Hsu; et al. (OFC, 2025)