7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology. - Mario Sako; Yoshihisa Watanabe; Takao Nakajima; Jumpei Sato; Kazuyoshi Muraoka; Masaki Fujiu; Fumihiro Kouno; Michio Nakagawa; Masami Masuda; Koji Kato; Yuri Terada; Yuki Shimizu; et al. (ISSCC, 2015)

A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology. - Mario Sako; Yoshihisa Watanabe; Takao Nakajima; Jumpei Sato; Kazuyoshi Muraoka; Masaki Fujiu; Fumihiro Kono; Michio Nakagawa; Masami Masuda; Koji Kato; Yuri Terada; Yuki Shimizu; et al. (IEEE J. Solid State Circuits, 2016)

A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology. - Hiroshi Maejima; Kazushige Kanda; Susumu Fujimura; Teruo Takagiwa; Susumu Ozawa; Jumpei Sato; Yoshihiko Shindo; Manabu Sato; Naoaki Kanagawa; Junji Musha; Satoshi Inoue; Katsuaki Sakurai; et al. (ISSCC, 2018)

13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs. - Toshiyuki Kouchi; Noriyasu Kumazaki; Masashi Yamaoka; Sanad Bushnaq; Takuyo Kodama; Yuki Ishizaki; Yoko Deguchi; Akio Sugahara; Akihiro Imamoto; Norichika Asaoka; Ryosuke Isomura; Takaya Handa; et al. (ISSCC, 2020)

A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs. - Toshiyuki Kouchi; Mami Kakoi; Noriyasu Kumazaki; Akio Sugahara; Akihiro Imamoto; Yasufumi Kajiyama; Yuri Terada; Sanad Bushnaq; Naoaki Kanagawa; Takuyo Kodama; Ryo Fukuda; Hiromitsu Komai; et al. (IEEE J. Solid State Circuits, 2021)

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os. - Kosuke Yanagidaira; Mario Sako; Yasuhiro Hirashima; Junya Matsuno; Yumi Higashi; Yutaka Shimizu; Akihiro Imamoto; Kazuaki Kawaguchi; Koji Tabata; Takeshi Nakano; Yusuke Ochi; Hiroaki Hoshino; et al. (ISSCC, 2025)