Akihisa Yamada

According to our database, Akihisa Yamada authored at least 12 papers between 1995 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Foreword.

Akihisa Yamada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

A multi-core architecture of digital back-end for large mutual capacitance touch sensing systems.

Akihisa Yamada, Yan Qian, Masayuki Yamaguchi, Hiroshi Honjoh, Takahiro Morishita, Shunsuke Nagasawa, Shinji Shinjo, Masayuki Miyamoto

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2006

C-based design of a real time speech recognition system.

Takashi Kambe, H. Matsuno, Y. Miyazaki, Akihisa Yamada

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004

C-based hardware design of IMDCT accelerator for Ogg Vorbis decoder.

Shinichi Maeta, Atsushi Kosaka, Akihisa Yamada, Takao Onoye, Toru Chiba, Isao Shirakawa

Proceedings of the 2004 12th European Signal Processing Conference, 2004

2002

Hardware Algorithm Optimization Using Bach C.

Kazuhisa Okada, Akihisa Yamada, Takashi Kambe

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001

A C-based synthesis system, Bach, and its application (invited talk).

Takashi Kambe, Akihisa Yamada, Koichi Nishida, Kazuhisa Okada, Mitsuhisa Ohnishi, Andrew Kay, Paul Boca, Vince Zammit, Toshio Nomura

Proceedings of ASP-DAC 2001, 2001

2000

Thread partitioning method for hardware compiler bach.

Mizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe

Proceedings of ASP-DAC 2000, 2000

1999

Hardware synthesis with the Bach system.

Akihisa Yamada, Koichi Nishida, Ryoji Sakurai, Andrew Kay, Toshio Nomura, Takashi Kambe

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler.

Ryoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihisa Yamada, Tetsuya Fujimoto, Takashi Kambe

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997

A method of redundant clocking detection and power reduction at RT level design.

Mitsuhisa Ohnishi, Akihisa Yamada, Hiroaki Noda, Takashi Kambe

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Architecture evaluation based on the datapath structure and parallel constraint.

Masayuki Yamaguchi, Akihisa Yamada, Toshihiro Nakaoka, Takashi Kambe

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1995

Optimal Scheduling for Conditional Recource Sharing.

Akihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995