A wafer-scale 170000-gate FFT processor with built-in test circuits. - Koichi Yamashita; Akinori Kanasugi; Shinpei Hijiya; Gensuke Goto; Nobutake Matsumura; Takehide Shirato (IEEE J. Solid State Circuits, 1988)

A digital application of chaotic oscillation modes in Josephson circuit. - Mititada Morisue; Masayuki Yamadaya; Hiroshi Noguchi; Akinori Kanasugi (Int. J. Intell. Syst., 1997)

A Genetic Algorithm for Switchbox Routing Problem. - Akinori Kanasugi; Takashi Shimayama; Naoshi Nakaya; Takeshi Iizuka (Rough Sets and Current Trends in Computing, 1998)

A Design of Architecture for Rough Set Processor. - Akinori Kanasugi (JSAI Workshops, 2001)

Genetic Algorithm that can Dynamically Change Number of Individuals and Accuracy. - Akihiko Tsukahara; Akinori Kanasugi (FBIT, 2007)

Design and Implementation of Rough Rules Generation from Logical Rules on FPGA Board. - Akinori Kanasugi; Mitsuhiro Matsumoto (RSEISP, 2007)

A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory. - Akinori Kanasugi; Akihiko Tsukahara (J. Convergence Inf. Technol., 2007)

Design of Dynamically Reconfigurable Processor for the H.264/AVC Image Prediction and De-blocking Filter. - Yuki Hayakawa; Akinori Kanasugi (CSE, 2010)

A dynamically reconfigurable processor for H.264/AVC image prediction. - Yuki Hayakawa; Akinori Kanasugi (Artif. Life Robotics, 2010)

A novel coding method for genetic algorithms based on redundant binary numbers. - Akira Murayama; Akinori Kanasugi (Artif. Life Robotics, 2010)

A Design and Simulation for Dynamically Reconfigurable Systolic Array. - Toshiyuki Ishimura; Akinori Kanasugi (Int. J. Inf. Process. Manag., 2010)

A Processor for Genetic Algorithm Based on Redundant Binary Number. - Masanao Aoshima; Akinori Kanasugi (J. Next Gener. Inf. Technol., 2010)

A Processor for GA based on Redundant Binary Number using FPGA. - Akira Murayama; Akinori Kanasugi (J. Next Gener. Inf. Technol., 2012)

Position detection method for microwell chip on microscope stage by photon multiplier tube. - Ki Ando; Hidekazu Uchida; Shamim Ahmed; Koichi Nishigaki; Osamu Takei; Akinori Kanasugi (Artif. Life Robotics, 2014)

Accuracy improvement of genetic algorithm for obtaining floating-point solution. - Kengo Nishijima; Akinori Kanasugi; Ki Ando (Artif. Life Robotics, 2014)

A novel architecture of dynamically reconfigurable fused multiply-adder for digital signal processing. - Akihiko Tsukahara; Akinori Kanasugi (Artif. Life Robotics, 2014)

Design of a Real Coded GA Processor. - Akihiko Tsukahara; Akinori Kanasugi (IJCCI (ECTA), 2015)

Generator of dynamically reconfigurable processor. - Takahiko Sega; Akinori Kanasugi; Ki Ando (Artif. Life Robotics, 2015)

Hardware implementation of evolutionary algorithms using dynamic reconfiguration technology. - Akinori Kanasugi; Akihiko Tsukahara; Ki Ando (Nat. Comput., 2015)

Design of Approximate Arithmetic Circuits within Tolerance. - Akihiko Tsukahara; Akinori Kanasugi (CEEC, 2018)

A design of EPIC type processor based on MIPS architecture. - Takahito Hayashi; Akinori Kanasugi (Artif. Life Robotics, 2020)

An integrated machine code monitor for a RISC-V processor on an FPGA. - Hiroaki Kaneko; Akinori Kanasugi (Artif. Life Robotics, 2020)