A 64-Mb DRAM with meshed power line. - Toshio Yamada; Yoshiro Nakata; Junko Hasegawa; Noriaki Amano; Akinori Shibayama; Masaru Sasago; Naoto Matsuo; Toshiki Yabu; Susumu Matsumoto; Shozo Okada; Michihiro Inoue (IEEE J. Solid State Circuits, 1991)

A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. - Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Masatoshi Ishikawa; Toshihiro Inokuchi; Hiroshi Kato; Hiroaki Tanizaki; Wataru Abe; Akinori Shibayama; Yoshifumi Fukushima; Mitsutaka Niiro; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2001)

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. - Hirohito Kikukawa; Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Shouji Sakamoto; Masatoshi Ishikawa; Wataru Abe; Hiroaki Tanizaki; Hiroshi Kato; Toshitaka Uchikoba; Toshihiro Inokuchi; Manabu Senoh; et al. (IEEE J. Solid State Circuits, 2002)

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. - Koji Nii; Yasumasa Tsukamoto; Tomoaki Yoshizawa; Susumu Imaoka; Yoshinobu Yamagami; Toshikazu Suzuki; Akinori Shibayama; Hiroshi Makino; Shuhei Iwade (IEEE J. Solid State Circuits, 2004)

0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. - Toshikazu Suzuki; Yoshinobu Yamagami; Ichiro Hatanaka; Akinori Shibayama; Hironori Akamatsu; Hiroyuki Yamauchi (IEICE Trans. Electron., 2005)

A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. - Toshikazu Suzuki; Yoshinobu Yamagami; Ichiro Hatanaka; Akinori Shibayama; Hironori Akamatsu; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2006)