LOTOS enhancement to specify time constraint among non-adjacent actions using first order logic. - Akio Nakata; Teruo Higashino; Kenichi Taniguchi (FORTE, 1993)

Verification of Liveness Property for Communicating FSM's with Conditional Transitions Depending on State Visiting Numbers. - Teruo Higashino; Akio Nakata; Tatsuo Itoh; Kenichi Taniguchi (FORTE, 1995)

Protocol synthesis from timed and structured specifications. - Akio Nakata; Teruo Higashino; Kenichi Taniguchi (ICNP, 1995)

Time-Action Alternating Model for Timed LOTOS and its Symbolic Verification of Bisimulation Equivalence. - Akio Nakata; Teruo Higashino; Kenichi Taniguchi (FORTE, 1996)

Protocol Synthesis from Context-Free Processes Using Event Structures. - Akio Nakata; Teruo Higashino; Kenichi Taniguchi (RTCSA, 1998)

Generating Test Cases for a Timed I/O Automaton Model. - Teruo Higashino; Akio Nakata; Kenichi Taniguchi; Ana R. Cavalli (IWTCS, 1999)

Deriving Parameter Conditions for Periodic Timed Automata Satisfying Real-Time Temporal Logic Formulas. - Akio Nakata; Teruo Higashino (FORTE, 2001)

A Conformance Testing Method for Communication Protocols Modeled as Concurrent DFSMs. - Atsushi Fukada; Akio Nakata; Junji Kitamichi; Teruo Higashino; Ana R. Cavalli (ICOIN, 2001)

A Language for Describing Wireless Mobile Applications with Dynamic Establishment of Multi-way Synchronization Channels. - Takaaki Umedu; Yoshiki Terashima; Keiichi Yasumoto; Akio Nakata; Teruo Higashino; Kenichi Taniguchi (FME, 2002)

Design and Implementation of FPGA Circuits for High Speed Network Monitors. - Masayuki Kirimura; Yoshifumi Takamoto; Takanori Mori; Keiichi Yasumoto; Akio Nakata; Teruo Higashino (FPL, 2002)

A Method for Functional Testing of Media Synchronization Protocols. - Makoto Yamada; Takanori Mori; Atsushi Fukada; Akio Nakata; Teruo Higashino (ICOIN (2), 2002)

Protocol animation based on event-driven visualization scenarios in real-time LOTOS. - Keiichi Yasumoto; Takaaki Umedu; Hirozumi Yamaguchi; Akio Nakata; Teruo Higashino (Comput. Networks, 2002)

Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking. - Tomoya Kitani; Yoshifumi Takamoto; Isao Naka; Keiichi Yasumoto; Akio Nakata; Teruo Higashino (FPL, 2003)

A test sequence generation method for communication protocols using the SAT algorithm. - Takanori Mori; Hirotaka Otsuka; Nobuo Funabiki; Akio Nakata; Teruo Higashino (Syst. Comput. Jpn., 2003)

A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata. - Tadaaki Tanimoto; Suguru Sasaki; Akio Nakata; Teruo Higashino (ATVA, 2004)

A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems. - Tomoya Kitani; Yoshifumi Takamoto; Keiichi Yasumoto; Akio Nakata; Teruo Higashino (RTSS, 2004)

A Method for Designing Multimedia Protocols using Both Parametric Model Checking and Functional Testing. - Takanori Mori; Akio Nakata; Teruo Higashino (Stud. Inform. Univ., 2004)

Automatic Decomposition of Java Program for Implementation on Mobile Terminals. - Takaaki Umedu; Shigeharu Urata; Akio Nakata; Teruo Higashino (AINA, 2005)

Double Depth First Search Based Parametric Analysis for Parametric Time-Interval Automata. - Tadaaki Tanimoto; Akio Nakata; Hideaki Hashimoto; Teruo Higashino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A real time budgeting method for module-level-pipelined bus based system using bus scenarios. - Tadaaki Tanimoto; Seiji Yamaguchi; Akio Nakata; Teruo Higashino (DAC, 2006)

A Timed Failure Equivalence Preserving Abstraction for Parametric Time-interval Automata. - Akio Nakata; Tadaaki Tanimoto; Suguru Sasaki; Teruo Higashino (Int. J. Found. Comput. Sci., 2006)

An Improved LLF Scheduling for Reducing Maximum Heap Memory Consumption by Considering Laxity Time. - Yuki Machigashira; Akio Nakata (TASE, 2018)