Architecture and Implementation of PIM/p. - Kouichi Kumon; Akira Asato; Susumu Arai; Tsuyoshi Shinogi; Akira Hattori; Hiroyoshi Hatazawa; Kiyoshi Hirano (FGCS, 1992)

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications. - Hajime Kubosawa; Hiromasa Takahashi; Satoshi Ando; Yoshimi Asada; Akira Asato; Atsuhiro Suga; Michihide Kimura; Naoshi Higaki; Hideo Miyake; Tomio Sato; Hideaki Anbutsu; Toshitaka Tsuda; et al. (IEEE J. Solid State Circuits, 1998)

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. - Hajime Kubosawa; Naoshi Higaki; Satoshi Ando; Hiromasa Takahashi; Yoshimi Asada; Hideaki Anbutsu; Tomio Sato; Masato Sakate; Atsuhiro Suga; Michihide Kimura; Hideo Miyake; Hiroshi Okano; et al. (IEEE J. Solid State Circuits, 1999)

Grid Service Platform: Design and Implementation of Grid Middleware for Telecom Carriers. - Soichi Shigeta; Nobutaka Imamura; Haruyasu Ueda; Hiromichi Kobashi; Miho Murata; Taketoshi Yoshida; Atsushi Kubota; Akira Asato; Yoshimasa Kadooka (e-Science, 2006)

A Case Study: Energy Efficient High Throughput Chip Multi-Processor Using Reduced-complexity Cores for Transaction Processing Workload. - Hisashige Ando; Akira Asato; Motoyuki Kawaba; Hideki Okawara; William W. Walker (Inf. Media Technol., 2006)

Evaluation of the RIKEN Post-K Processor Simulator. - Yuetsu Kodama; Tetsuya Odajima; Akira Asato; Mitsuhisa Sato (CoRR, 2019)

Accuracy Improvement of Memory System Simulation for Modern Shared Memory Processor. - Yuetsu Kodama; Tetsuya Odajima; Akira Asato; Mitsuhisa Sato (HPC Asia, 2020)

Co-design for A64FX manycore processor and "Fugaku". - Mitsuhisa Sato; Yutaka Ishikawa; Hirofumi Tomita; Yuetsu Kodama; Tetsuya Odajima; Miwako Tsuji; Hisashi Yashiro; Masaki Aoki; Naoyuki Shida; Ikuo Miyoshi; Kouichi Hirai; Atsushi Furuya; et al. (SC, 2020)