An acceleration of a random forest classification using Altera SDK for OpenCL. - Hiroki Nakahara; Akira Jinguji; Tomonori Fujii; Simpei Sato (FPT, 2016)

A Random Forest Using a Multi-valued Decision Diagram on an FPGA. - Hiroki Nakahara; Akira Jinguji; Simpei Sato; Tsutomu Sasao (ISMVL, 2017)

An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network. - Akira Jinguji; Tomoya Fujii; Shimpei Sato; Hiroki Nakahara (FPT, 2018)

An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design. - Akira Jinguji; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2018)

An FPGA-based Fine Tuning Accelerator for a Sparse CNN. - Hiroki Nakahara; Akira Jinguji; Masayuki Shimoda; Shimpei Sato (FPGA, 2019)

Real-Time Multi-Pedestrian Detection in Surveillance Camera using FPGA. - Akira Jinguji; Youki Sada; Hiroki Nakahara (FPL, 2019)

FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. - Hiroki Nakahara; Youki Sada; Masayuki Shimoda; Kouki Sayama; Akira Jinguji; Shimpei Sato (FPL, 2019)

A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA. - Youki Sada; Masayuki Shimoda; Akira Jinguji; Hiroki Nakahara (FPT, 2019)

Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. - Akira Jinguji; Shimpei Sato; Hiroki Nakahara (FCCM, 2020)

R2CNN: Recurrent Residual Convolutional Neural Network on FPGA. - Hiroki Nakahara; Zhiqiang Que; Akira Jinguji; Wayne Luk (FPGA, 2020)

Fast Monocular Depth Estimation on an FPGA. - Youki Sada; Naoto Soga; Masayuki Shimoda; Akira Jinguji; Shimpei Sato; Hiroki Nakahara (IPDPS Workshops, 2020)

Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs. - Akira Jinguji; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2021)

Multilayer Perceptron Training Accelerator Using Systolic Array. - Takeshi Senoo; Akira Jinguji; Ryosuke Kuramochi; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2022)

A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA. - Takeshi Senoo; Ryota Kayanoma; Akira Jinguji; Hiroki Nakahara (ARC, 2023)

A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference. - Ryota Kayanoma; Akira Jinguji; Hiroki Nakahara (MCSoC, 2023)