VLSI processor for image processing. - Masamichi Sugai; Akira Kanuma; Kaoru Suzuki; Moritada Kubo (Proc. IEEE, 1987)

A CMOS 510 K-transistor single-chip token-ring LAN controller (TRC) compatible with IEEE802.5 MAC protocol. - Akira Kanuma; Toshiyuki Yaguchi; Koichi Tanaka; Eiichi Katsumata; Katsuhito Fujimoto; Yuuichi Miyazawa; Shinichi Iida; Takeshi Yamamoto (IEEE J. Solid State Circuits, 1990)

Detection of multiple transitions in delay fault test of SPARC64 microprocessor. - Daisuke Maruyama; Akira Kanuma; Takashi Mochiyama; Hiroaki Komatsu; Yaroku Sugiyama; Noriyuki Ito (ICCAD, 2004)

Delay defect screening for a 2.16GHz SPARC64 microprocessor. - Noriyuki Ito; Akira Kanuma; Daisuke Maruyama; Hitoshi Yamanaka; Tsuyoshi Mochizuki; Osamu Sugawara; Chihiro Endoh; Masahiro Yanagida; Takeshi Kono; Yutaka Isoda; Kazunobu Adachi; Takahisa Hiraide; et al. (ASP-DAC, 2006)

Design Methodology for 2.4GHz Dual-Core Microprocessor. - Noriyuki Ito; Hiroaki Komatsu; Akira Kanuma; Akihiro Yoshitake; Yoshiyasu Tanamura; Hiroyuki Sugiyama; Ryoichi Yamashita; Ken-ichi Nabeya; Hironobu Yoshino; Hitoshi Yamanaka; Masahiro Yanagida; Yoshitomo Ozeki; et al. (ASP-DAC, 2007)