A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations. - Akira Katsuno; Hiromasa Takahashi; Hajime Kubosawa; Tomio Sato; Atsuhiro Suga; Gensuke Goto (ICCD, 1990)

Microarchitecture of HaL's CPU. - Niteen Patkar; Akira Katsuno; Simon Li; Tak Maruyama; Sunil Savkar; Mike Simone; Gene Shen; Ravi Swami; DeForest Tovey (COMPCON, 1995)

Reverse Tracer: A Software Tool for Generating Realistic Performance Test Programs. - Mariko Sakamoto; Larry Brisson; Akira Katsuno; Aiichiro Inoue; Yasunori Kimura (HPCA, 2002)

Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems. - Mariko Sakamoto; Akira Katsuno; Aiichiro Inoue; Takeo Asakawa; Haruhiko Ueno; Kuniki Morita; Yasunori Kimura (HPCA, 2003)

A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips. - Mariko Sakamoto; Akira Katsuno; Go Sugizaki; Toshio Yoshida; Aiichiro Inoue; Koji Inoue; Kazuaki J. Murakami (IEICE Trans. Electron., 2007)