Hardware synthesis from protocol specifications in LOTOS. - Keiichi Yasumoto; Akira Kitajima; Teruo Higashino; Kenichi Taniguchi (FORTE, 1998)

Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization. - Hisaaki Katagiri; Keiichi Yasumoto; Akira Kitajima; Teruo Higashino; Kenichi Taniguchi (DAC, 2000)

PEAS-III: An ASIP Design Environment. - Makiko Itoh; Shigeaki Higaki; Yoshinori Takeuchi; Akira Kitajima; Masaharu Imai; Jun Sato; Akichika Shiomi (ICCD, 2000)

Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. - Akira Kitajima; Makiko Itoh; Jun Sato; Akichika Shiomi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2001)

Formal Verification of CPU in Laboratory Work. - Kozo Okano; Yuko Kitahama; Akira Kitajima; Teruo Higashino; Kenichi Taniguchi (MSE, 2001)

Design of Application Specific CISC Using PEAS-III. - Akira Kitajima; Toshiyuki Sasaki; Yoshinori Takeuchi; Masaharu Imai (IEEE International Workshop on Rapid System Prototyping, 2002)

Verification Challenges in Configurable Processor Design with ASIP Meister. - Masaharu Imai; Akira Kitajima (CHARME, 2005)