Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons. - Moritoshi Yasunaga; Noboru Masuda; Masayoshi Yagyu; Mitsuo Asai; Minoru Yamada; Akira Masaki (IJCNN, 1990)

Possibilities of deep-submicrometer CMOS for very-high-speed computer logic. - Akira Masaki (Proc. IEEE, 1993)

FPGAs with Multidimensional Switch Topology. - Yohei Matsumoto; Akira Masaki (IEICE Trans. Inf. Syst., 2005)

FPGAs with multidimensional mesh topology. - Yohei Matsumoto; Hanpei Koike; Akira Masaki (FPGA, 2006)