A 10-b 300-MHz interpolated-parallel A/D converter. - Hiroshi Kimura; Akira Matsuzawa; Takashi Nakamura; Shigeki Sawada (IEEE J. Solid State Circuits, 1993)

A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC. - Keiichi Kusumoto; Akira Matsuzawa; Kenji Murata (IEEE J. Solid State Circuits, 1993)

Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment. - Akira Matsuzawa (IEEE J. Solid State Circuits, 1994)

A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. - Hiroyuki Yamauchi; Toru Iwata; Hironori Akamatsu; Akira Matsuzawa (ISLPED, 1996)

A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme. - Hiroyuki Yamauchi; Akira Matsuzawa (IEEE J. Solid State Circuits, 1996)

Design, Fabrications and Use of Mixed-Signal IC Testability Structures. - Kenneth P. Parker; John E. McDermid; Rodney A. Browen; Kozo Nuriya; Katsuhiro Hirayama; Akira Matsuzawa (ITC, 1997)

A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras. - Shoji Kawahito; Makoto Yoshida; Masaaki Sasaki; Keijiro Umehara; Daisuke Miyazaki; Yoshiaki Tadokoro; Kenji Murata; Shiro Doushou; Akira Matsuzawa (IEEE J. Solid State Circuits, 1997)

A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. - Hiroyuki Yamauchi; Toru Iwata; Hironori Akamatsu; Akira Matsuzawa (IEEE Trans. Very Large Scale Integr. Syst., 1997)

CMOS Image Sensors with Video Compression. - Shoji Kawahito; Yoshiaki Tadokoro; Akira Matsuzawa (ASP-DAC, 1998)

A CMOS Smart Image Sensor LSI for Focal-Plane Compression. - Shoji Kawahito; Makoto Yoshida; Masaaki Sasaki; Daisuke Miyazaki; Yoshiaki Tadokoro; Kenji Murata; Shiro Doushou; Akira Matsuzawa (ASP-DAC, 1998)

A CMOS Image Sensor with Non-Destructive High-Speed Imaging Mode and Its Applications. - Dwi Handoko; Shoji Kawahito; Minoru Kumahara; Nobuhiro Kawai; Yoshiaki Tadokoro; Akira Matsuzawa (J. Robotics Mechatronics, 2000)

High Quality Analog CMOS and Mixed Signal LSI Design. - Akira Matsuzawa (ISQED, 2001)

A mixed-signal 0.18-μm CMOS SoC for DVD systems with 432-MSample/s PRML read channel and 16-Mb embedded DRAM. - Takashi Yamamoto; Shin-Ichi Gotoh; Toshihiko Takahashi; Kozo Irie; Kazuya Ohshima; Nobuhiro Mimura; Kazutoshi Aida; Toshinori Maeda; Koji Sushihara; Yoichi Okamoto; Yasuhiro Tai; Makoto Usui; et al. (IEEE J. Solid State Circuits, 2001)

Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor. - Dwi Handoko; Shoji Kawahito; Yoshiaki Tadokoro; Akira Matsuzawa (IEEE Trans. Circuits Syst. Video Technol., 2002)

How to make efficient communication, collaboration, and optimization from system to chip. - Akira Matsuzawa (DAC, 2003)

Driving the SoC developments for digital consumer electronics. - Akira Matsuzawa (ESTIMedia, 2003)

A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications. - Koji Okamoto; Takashi Morie; Akira Yamamoto; Kouichi Nagano; Koji Sushihara; Hiroyuki Nakahira; Ryusuke Horibe; Kazutoshi Aida; Toshihiko Takahashi; Minoru Ochiai; Akinobu Soneda; Toru Kakiage; et al. (IEEE J. Solid State Circuits, 2003)

A background optimization method for PLL by measuring phase jitter performance. - Shiro Dosho; Naoshi Yanagisawa; Akira Matsuzawa (IEEE J. Solid State Circuits, 2005)

Feedforward compensation technique for all digital phase locked loop based synthesizers. - Win Chaivipas; Akira Matsuzawa; Philipus Chandra Oh (ISCAS, 2006)

Analog IC Technologies for Future Wireless Systems. - Akira Matsuzawa (IEICE Trans. Electron., 2006)

Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop. - Win Chaivipas; Akira Matsuzawa (IEICE Trans. Electron., 2007)

Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC. - Yusuke Ikeda; Akira Matsuzawa (IEICE Trans. Electron., 2007)

Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS. - Akira Matsuzawa (IEICE Trans. Electron., 2007)

The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time. - Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2007)

A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter. - Philipus Chandra Oh; Akira Matsuzawa; Win Chaivipas (IEICE Trans. Electron., 2007)

A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio. - Hong Phuc Ninh; Takashi Moue; Takashi Kurashina; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2008)

"The flipped voltage follower"-based low voltage fully differential CMOS sample-and-hold circuit. - Christian Jesús B. Fayomi; Gilson I. Wirth; Jaime Ramírez-Angulo; Akira Matsuzawa (ISCAS, 2008)

Design space exploration of low-phase-noise LC-VCO using multiple-divide technique. - Shoichi Hara; Takeshi Ito; Kenichi Okada 001; Akira Matsuzawa (ISCAS, 2008)

Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators. - Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2008)

RF Variable-Gain Amplifiers and AGC Loops for Digital TV Receivers. - Kunihiko Iizuka; Masato Koutani; Takeshi Mitsunaka; Hiroshi Kawamura; Shinji Toyoyama; Masayuki Miyamoto; Akira Matsuzawa (IEICE Trans. Electron., 2008)

Analysis of CMOS Transconductance Amplifiers for Sampling Mixers. - Ning Li 009; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2008)

Digital-Centric RF CMOS Technologies. - Akira Matsuzawa (IEICE Trans. Electron., 2008)

A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing. - Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS. - Christian Jesús B. Fayomi; Gilson I. Wirth; David M. Binkley; Akira Matsuzawa (ICECS, 2009)

Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof. - Kaziiya Kojima; Yasuhiro Toriyama; Toru Taniguchi; Masaya Miyahara; Akira Matsuzawa (ICECS, 2009)

A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-µm CMOS. - Yasuhide Kuramochi; Akira Matsuzawa; Masayuki Kawabata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters. - Daisuke Imanishi; Jee Young Hong; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2010)

A 60GHz direct-conversion transmitter in 65nm CMOS technology. - Naoki Takayama; Kota Matsushita; Shogo Ito; Ning Li 009; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2010)

A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors. - Ning Li 009; Keigo Bunsen; Naoki Takayama; Qinghong Bu; Toshihide Suzuki; Masaru Sato 001; Tatsuya Hirose; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2010)

The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique. - Shoichi Hara; Rui Murakami; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider. - Shoichi Hara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2010)

A Self-Calibration Technique for Capacitor Mismatch Errors of an Interleaved SAR ADC. - Yasuhide Kuramochi; Masayuki Kawabata; Koichiro Uekusa; Akira Matsuzawa (IEICE Trans. Electron., 2010)

Evaluation of a Multi-Line De-Embedding Technique up to 110 GHz for Millimeter-Wave CMOS Circuit Design. - Ning Li 009; Kota Matsushita; Naoki Takayama; Shogo Ito; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators. - Rui Murakami; Shoichi Hara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2010)

An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques. - Daehwa Paik; Yusuke Asada; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling. - Naoki Takayama; Kota Matsushita; Shogo Ito; Ning Li 009; Keigo Bunsen; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2010)

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator. - Kazuo Matsukawa; Yosuke Mitani; Masao Takayama; Koji Obata; Shiro Dosho; Akira Matsuzawa (IEEE J. Solid State Circuits, 2010)

Energy efficient ADC design with low voltage operation. - Akira Matsuzawa (ASICON, 2011)

An analysis on a pseudo-differential dynamic comparator with load capacitance calibration. - Daehwa Paik; Masaya Miyahara; Akira Matsuzawa (ASICON, 2011)

A new figure of Merit of LC oscilators considering frequency tuning range. - Takahiro Sato; Kenichi Okada 001; Akira Matsuzawa (ASICON, 2011)

An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2011)

A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique. - Ahmed Musa; Rui Murakami; Takahiro Sato; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2011)

A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS. - Hiroki Asada; Keigo Bunsen; Kota Matsushita; Rui Murakami; Qinghong Bu; Ahmed Musa; Takahiro Sato; Tatsuya Yamaguchi; Ryo Minami; Toshihiko Ito; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2011)

A 20GHz ILFD with locking range of 31% for divide-by-4 and 15% for divide-by-8 using progressive mixing. - Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2011)

A time-domain architecture and design method of high speed A-to-D converters with standard cells. - Masao Takayama; Shiro Dosho; Noriaki Takeda; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2011)

A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2011)

A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique. - James Lin; Masaya Miyahara; Akira Matsuzawa (ISCAS, 2011)

A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c. - Kenichi Okada 001; Kota Matsushita; Keigo Bunsen; Rui Murakami; Ahmed Musa; Takahiro Sato; Hiroki Asada; Naoki Takayama; Ning Li 009; Shogo Ito; Win Chaivipas; Ryo Minami; et al. (ISSCC, 2011)

A 14.3% PAE parallel class-A and AB 60GHz CMOS PA. - Ning Li 009; Kota Matsushita; Kenichi Okada 001; Akira Matsuzawa (IEICE Electron. Express, 2011)

An ultra-compact LC-VCO using a stacked-spiral inductor. - Rui Murakami; Toshihiko Ito; Kenichi Okada 001; Akira Matsuzawa (IEICE Electron. Express, 2011)

Tunable CMOS Power Amplifiers for Reconfigurable Transceivers. - Jee Young Hong; Daisuke Imanishi; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Topology and Design Considerations of 60 GHz CMOS LNAs for Noise Performance Improving. - Ning Li 009; Qinghong Bu; Kota Matsushita; Naoki Takayama; Shogo Ito; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2011)

Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip. - Ryo Minami; Jee Young Hong; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2011)

A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications. - Ahmed Musa; Rui Murakami; Takahiro Sato; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2011)

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c. - Kenichi Okada 001; Ning Li 009; Kota Matsushita; Keigo Bunsen; Rui Murakami; Ahmed Musa; Takahiro Sato; Hiroki Asada; Naoki Takayama; Shogo Ito; Win Chaivipas; Ryo Minami; et al. (IEEE J. Solid State Circuits, 2011)

A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2012)

A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS. - Ryo Minami; Hiroki Asada; Ahmed Musa; Takahiro Sato; Ning Li 009; Tatsuya Yamaguchi; Yasuaki Takeuchi; Win Chaivipas; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2012)

A Progressive Mixing 20GHz ILFD with wide locking range for higher division ratios. - Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2012)

A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. - Wei Deng 001; Teerachot Siriburanon; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2012)

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. - Kenichi Okada 001; Keitarou Kondou; Masaya Miyahara; Masashi Shinagawa; Hiroki Asada; Ryo Minami; Tatsuya Yamaguchi; Ahmed Musa; Yuuki Tsukui; Yasuo Asakura; Shinya Tamonoki; Hiroyuki Yamagishi; et al. (ISSCC, 2012)

Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design. - Qinghong Bu; Ning Li 009; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2012)

A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2012)

Two-Stage Band-Selectable CMOS Power Amplifiers Using Inter-Stage Frequency Tuning. - Jee Young Hong; Daisuke Imanishi; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2012)

Inter-Stage Tunable Notch Filter for a Multi-Band WCDMA Receiver. - Toshihiko Ito; Masaki Kanemaru; Satoshi Furuya; Dong Ta Ngoc Huy; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2012)

A Wideband Common-Gate Low-Noise Amplifier Using Capacitive Feedback. - Toshihiko Ito; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2012)

A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors. - Ning Li 009; Keigo Bunsen; Naoki Takayama; Qinghong Bu; Toshihide Suzuki; Masaru Sato 001; Yoichi Kawano; Tatsuya Hirose; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching. - Hong Phuc Ninh; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2012)

A Dual-Conduction Class-C VCO for a Low Supply Voltage. - Kenichi Okada 001; You Nomiyama; Rui Murakami; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator. - Daehwa Paik; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A Specific Distortion Pattern of Flash ADCs Identified by Discriminating Time-Domain Analysis. - Yuji Gendai; Akira Matsuzawa (IEEE Trans. Instrum. Meas., 2012)

A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios. - Wei Deng 001; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2013)

A full 4-channel 60 GHz direct-conversion transceiver. - Seitaro Kawai; Ryo Minami; Ahmed Musa; Takahiro Sato; Ning Li 009; Tatsuya Yamaguchi; Yasuaki Takeuchi; Yuki Tsukui; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2013)

A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. - Teerachot Siriburanon; Wei Deng 001; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2013)

A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers. - James Lin; Daehwa Paik; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (CICC, 2013)

A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC. - Zule Xu; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (CICC, 2013)

A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. - Teerachot Siriburanon; Wei Deng 001; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2013)

A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. - Wei Deng 001; Ahmed Musa; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2013)

A 60 GHz up-conversion mixer using asymmetric layout with -41.1 dBc LO leakage. - Yuki Tsukui; Kenichi Okada 001; Akira Matsuzawa (LASCAS, 2013)

A 12-bit interpolated pipeline ADC using body voltage controlled amplifier. - Hyunui Lee; Masaya Miyahara; Akira Matsuzawa (NEWCAS, 2013)

A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS. - Zule Xu; Masaya Miyahara; Akira Matsuzawa (NEWCAS, 2013)

A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation. - Hyunui Lee; Yusuke Asada; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers. - Hyunui Lee; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2013)

Design of CMOS Low-Noise Analog Circuits for Particle Detector Pixel Readout LSIs. - Fei Li; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2013)

A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs. - Fei Li; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2013)

A Study of Stability and Phase Noise of Tail Capacitive-Feedback VCOs. - Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2013)

A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer. - Teerachot Siriburanon; Takahiro Sato; Ahmed Musa; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2013)

Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing. - Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2013)

A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. - Wei Deng 001; Teerachot Siriburanon; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2013)

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry. - Kenichi Okada 001; Keitarou Kondou; Masaya Miyahara; Masashi Shinagawa; Hiroki Asada; Ryo Minami; Tatsuya Yamaguchi; Ahmed Musa; Yuuki Tsukui; Yasuo Asakura; Shinya Tamonoki; Hiroyuki Yamagishi; et al. (IEEE J. Solid State Circuits, 2013)

A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. - Wei Deng 001; Ahmed Musa; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2014)

A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. - Teerachot Siriburanon; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2014)

A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier. - James Lin; Zule Xu; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2014)

A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI. - Aravind Tharayil Narayanan; Wei Deng 001; Dongsheng Yang 002; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2014)

A 0.015-mm2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs. - Rui Wu 001; Qinghong Bu; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2014)

A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz. - Aravind Tharayil Narayanan; Kento Kimura; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2014)

Radio receiver front-end using time-based all-digital ADC (TAD). - Tomohito Terasawa; Yuji Kamiya; Hiroyuki Kawashima; Kenichiro Imai; Masanobu Suzuki; Takamoto Watanabe; Nobuyuki Taguchi; Manabu Sawada; Yu Hou; Yoshiyuki Hirooka; Hong Phuc Ninh; Masaya Miyahara; et al. (ICECS, 2014)

All-digital 0.016mm2 reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS. - Takamoto Watanabe; Yu Hou; Masaya Miyahara; Akira Matsuzawa (ICECS, 2014)

15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. - Wei Deng 001; Dongsheng Yang 002; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2014)

22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers. - Masaya Miyahara; Ibuki Mano; Masaaki Nakayama; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2014)

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding. - Kenichi Okada 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Yasuaki Takeuchi; Tatsuya Yamaguchi; Ahmed Musa; Rui Wu 001; et al. (ISSCC, 2014)

Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator. - Jeonghoon Han; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2014)

An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique. - James Lin; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A 7-bit 1-GS/s Flash ADC with Background Calibration. - Sanroku Tsukamoto; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2014)

A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation. - Rui Wu 001; Yuuki Tsukui; Ryo Minami; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2014)

A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios. - Wei Deng 001; Shoichi Hara; Ahmed Musa; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2014)

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. - Ahmed Musa; Wei Deng 001; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2014)

A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (ASICON, 2015)

Automated design strategy for high performance mixed signal circuits. - Akira Matsuzawa (ASICON, 2015)

A tail-current modulated VCO with adaptive-bias scheme. - Aravind Tharayil Narayanan; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. - Teerachot Siriburanon; Tomohiro Ueno; Kento Kimura; Satoshi Kondo; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

An HDL-synthesized gated-edge-injection PLL with a current output DAC. - Dongsheng Yang 002; Wei Deng 001; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2015)

A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise. - Zule Xu; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2015)

A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers. - Lilan Yu; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2015)

A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB. - Aravind Tharayil Narayanan; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Korkut Kaan Tokgoz; Kengo Nakata; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2015)

A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. - Teerachot Siriburanon; Hanli Liu; Kengo Nakata; Wei Deng 001; Ju Ho Son; Dae Young Lee; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2015)

Substrate noise isolation improvement by helium-3 ion irradiation technique in a triple-well CMOS process. - Ning Li 009; Takeshi Inoue; Takuichi Hirano; Jian Pang; Rui Wu 001; Kenichi Okada 001; Hitoshi Sakane; Akira Matsuzawa (ESSDERC, 2015)

High data rate 60 GHz CMOS transceiver design. - Akira Matsuzawa (ISPACS, 2015)

14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique. - Wei Deng 001; Dongsheng Yang 002; Aravind Tharayil Narayanan; Kengo Nakata; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2015)

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2015)

19.5 An HCI-healing 60GHz CMOS transceiver. - Rui Wu 001; Seitaro Kawai; Yuuki Seo; Kento Kimura; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; Yasuaki Takeuchi; Tatsuya Yamaguchi; et al. (ISSCC, 2015)

A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC. - Zhijie Chen; Masaya Miyahara; Akira Matsuzawa (VLSIC, 2015)

A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. - Dongsheng Yang 002; Wei Deng 001; Aravind Tharayil Narayanan; Rui Wu 001; Bangan Liu; Kenichi Okada 001; Akira Matsuzawa (IEICE Electron. Express, 2015)

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology. - Yu Hou; Takamoto Watanabe; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency. - Tohru Kaneko; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2015)

An AM-PM Noise Mitigation Technique in Class-C VCO. - Kento Kimura; Aravind Tharayil Narayanan; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2015)

A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. - Teerachot Siriburanon; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2015)

Characterization of Crossing Transmission Line Using Two-Port Measurements for Millimeter-Wave CMOS Circuit Design. - Korkut Kaan Tokgoz; Kimsrun Lim; Seitarou Kawai; Nurul Fajri; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2015)

A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections. - Rui Wu 001; Wei Deng 001; Shinji Sato; Takuichi Hirano; Ning Li 009; Takeshi Inoue; Hitoshi Sakane; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2015)

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC. - Zule Xu; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. - Wei Deng 001; Dongsheng Yang 002; Tomohiro Ueno; Teerachot Siriburanon; Satoshi Kondo; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2015)

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers. - James Lin; Daehwa Paik; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (IEEE J. Solid State Circuits, 2015)

Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product. - James Lin; Ibuki Mano; Masaya Miyahara; Akira Matsuzawa (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. - Aravind Tharayil Narayanan; Makihiko Katsuragi; Kengo Nakata; Yuki Terashima; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2016)

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. - Dongsheng Yang 002; Wei Deng 001; Aravind Tharayil Narayanan; Kengo Nakata; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2016)

A 2nd order fully-passive noise-shaping SAR ADC with embedded passive gain. - Zhijie Chen; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2016)

An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation. - Rui Wu 001; Jian Pang; Yuuki Seo; Kento Kimura; Seitaro Kawai; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Yasuaki Takeuchi; Tatsuya Yamaguchi; Ahmed Musa; et al. (A-SSCC, 2016)

A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers. - Lilan Yu; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2016)

A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder. - Zhijie Chen; Masaya Miyahara; Akira Matsuzawa (ESSCIRC, 2016)

A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter. - Tohru Kaneko; Yuya Kimura; Koji Hirose; Masaya Miyahara; Akira Matsuzawa (ESSCIRC, 2016)

A 2 GHz 3.1 mW type-I digital ring-based PLL. - Zule Xu; Anugerah Firdauzi; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2016)

An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2016)

A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. - Anugerah Firdauzi; Zule Xu; Masaya Miyahara; Akira Matsuzawa (ISCAS, 2016)

13.3 A 56Gb/s W-band CMOS wireless transceiver. - Korkut Kaan Tokgoz; Shotaro Maki; Seitaro Kawai; Noriaki Nagashima; Jun Emmei; Masato Dome; Hisashi Kato; Jian Pang; Yoichi Kawano; Toshihide Suzuki; Taisuke Iwai; Yuuki Seo; et al. (ISSCC, 2016)

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. - Rui Wu 001; Seitaro Kawai; Yuuki Seo; Nurul Fajri; Kento Kimura; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Teerachot Siriburanon; Shoutarou Maki; Bangan Liu; Yun Wang 008; et al. (ISSCC, 2016)

A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2016)

Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC. - Zhijie Chen; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2016)

A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology. - Yu Hou; Zhijie Chen; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. - Mitsutoshi Sugawara; Kenji Mori; Zule Xu; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI. - Dongsheng Yang 002; Tomohiro Ueno; Wei Deng 001; Yuki Terashima; Kengo Nakata; Aravind Tharayil Narayanan; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2016)

Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques. - Lilan Yu; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2016)

A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB. - Aravind Tharayil Narayanan; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Korkut Kaan Tokgoz; Kengo Nakata; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. - Teerachot Siriburanon; Satoshi Kondo; Makihiko Katsuragi; Hanli Liu; Kento Kimura; Wei Deng 001; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. - Zule Xu; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers. - Lilan Yu; Masaya Miyahara; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier. - Akira Matsuzawa; Masaya Miyahara (ASICON, 2017)

Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. - Rui Wu 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Kento Kimura; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; et al. (ASICON, 2017)

W-band ultra-high data-rate 65nm CMOS wireless transceiver. - Korkut Kaan Tokgoz; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yoichi Kawano; Toshihide Suzuki; Taisuke Iwai; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2017)

An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. - Dongsheng Yang 002; Wei Deng 001; Bangan Liu; Aravind Tharayil Narayanan; Teerachot Siriburanon; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2017)

A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2017)

An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier. - Masaya Miyahara; Akira Matsuzawa (CICC, 2017)

An automatic dynamic range adaptation algorithm for capacitive sensor interface circuits. - Tuan Minh Vo; Akira Matsuzawa (ECCTD, 2017)

A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (ESSCIRC, 2017)

8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. - Huy Cu Ngo; Kengo Nakata; Toru Yoshioka; Yuki Terashima; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2017)

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (ISSCC, 2017)

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. - Anugerah Firdauzi; Zule Xu; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2017)

A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input. - Tohru Kaneko; Yuya Kimura; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2017)

A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. - Aravind Tharayil Narayanan; Wei Deng 001; Dongsheng Yang 002; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2017)

Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs. - Mitsutoshi Sugawara; Zule Xu; Akira Matsuzawa (IEICE Trans. Electron., 2017)

A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256 QAM Wireless Transmission in 65-nm CMOS. - Yun Wang 008; Makihiko Katsuragi; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2017)

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. - Rui Wu 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Kento Kimura; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; et al. (IEEE J. Solid State Circuits, 2017)

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. - Bangan Liu; Huy Cu Ngo; Kengo Nakata; Wei Deng 001; Yuncheng Zhang; Junjun Qiu; Toru Yoshioka; Jun Emmei; Haosheng Zhang; Jian Pang; Aravind Tharayil Narayanan; Dongsheng Yang 002; et al. (CICC, 2018)

A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS. - Jian Sen Teh; Liter Siek; Abdel Martinez Alonso; Anugerah Firdauzi; Akira Matsuzawa (ISCAS, 2018)

An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. - Hanli Liu; Zheng Sun 001; Dexian Tang; Hongye Huang; Tohru Kaneko; Wei Deng 001; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2018)

A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. - Hanli Liu; Dexian Tang; Zheng Sun 001; Wei Deng 001; Huy Cu Ngo; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2018)

A 120Gb/s 16QAM CMOS millimeter-wave wireless transceiver. - Korkut Kaan Tokgoz; Shotaro Maki; Jian Pang; Noriaki Nagashima; Ibrahim Abdo; Seitaro Kawai; Takuya Fujimura; Yoichi Kawano; Toshihide Suzuki; Taisuke Iwai; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2018)

A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier. - Masaya Miyahara; Yukiya Endo; Kenichi Okada 001; Akira Matsuzawa (VLSI Circuits, 2018)

SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier. - Akira Matsuzawa; Masaya Miyahara (IEICE Electron. Express, 2018)

Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS. - Korkut Kaan Tokgoz; Seitaro Kawai; Kenichi Okada 001; Akira Matsuzawa (IEICE Electron. Express, 2018)

A 7GS/s Complete-DDFS-Solution in 65nm CMOS. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits. - Tohru Kaneko; Koji Hirose; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells. - Tohru Kaneko; Yuya Kimura; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. - Hanli Liu; Teerachot Siriburanon; Kengo Nakata; Wei Deng 001; Ju Ho Son; Dae Young Lee; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS. - Bangan Liu; Yun Wang 008; Jian Pang; Haosheng Zhang; Dongsheng Yang 002; Aravind Tharayil Narayanan; Dae Young Lee; Sung Tae Choi; Rui Wu 001; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (IEEE J. Solid State Circuits, 2018)

A Universal ADC for Sensor Applications. - Akira Matsuzawa (3DIC, 2019)

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. - Zule Xu; Anugerah Firdauzi; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2019)

A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS. - Yun Wang 008; Bangan Liu; Rui Wu 001; Hanli Liu; Aravind Tharayil Narayanan; Jian Pang; Ning Li 009; Toru Yoshioka; Yuki Terashima; Haosheng Zhang; Dexian Tang; Makihiko Katsuragi; et al. (IEEE J. Solid State Circuits, 2019)

Shape the World with Mixed-Signal Integrated Circuits - Past, Present, and Future. - Akira Matsuzawa (ISSCC, 2023)

Sampling circuit issues in A/D converters and challenges for the solution. - Akira Matsuzawa (IEICE Electron. Express, 2023)

A Brief History of Nyquist Analog-to-Digital Converters. - Akira Matsuzawa (IEICE Trans. Electron., 2023)