Verification of RTL generated from scheduled behavior in a high-level synthesis flow. - Pranav Ashar; Subhrajit Bhattacharya; Anand Raghunathan; Akira Mukaiyama (ICCAD, 1998)

Property-specific witness graph generation for guided simulation. - Albert E. Casavant; Aarti Gupta; S. Liu; Akira Mukaiyama; Kazutoshi Wakabayashi; Pranav Ashar (DATE, 2001)

Property-Specific Testbench Generation for Guided Simulation. - Aarti Gupta; Albert E. Casavant; Pranav Ashar; Sean Liu; Akira Mukaiyama; Kazutoshi Wakabayashi (ASP-DAC/VLSI Design, 2002)

Synthesizing "Verification Aware" Models: Why and How? - Malay K. Ganai; Akira Mukaiyama; Aarti Gupta; Kazutoshi Wakabayashi (VLSI Design, 2007)