A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator. - Akira Shikata; Ryota Sekimoto; Hiroki Ishikuro (APCCAS, 2010)

A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator. - Ryota Sekimoto; Akira Shikata; Tadahiro Kuroda; Hiroki Ishikuro (ESSCIRC, 2011)

An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (ESSCIRC, 2012)

A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. - Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2012)

A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (ASP-DAC, 2013)

An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS. - Ryota Sekimoto; Akira Shikata; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro (IEICE Trans. Electron., 2013)

A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller. - Akira Shikata; Ryota Sekimoto; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. - Ryota Sekimoto; Akira Shikata; Kentaro Yoshioka; Tadahiro Kuroda; Hiroki Ishikuro (IEEE J. Solid State Circuits, 2013)

An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (ASP-DAC, 2014)

An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS. - Kentaro Yoshioka; Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 12-Bit 31.1UW 1MS/S SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4DB SFDR Using 256FF Sampling Capacitance. - Junhua Shen; Akira Shikata; Anping Liu; Frederick Chalifoux (VLSI Circuits, 2018)

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS. - Junhua Shen; Akira Shikata; Lalinda Fernando; Ned Guthrie; Baozhen Chen; Mark Maddox; Nikhil Mascarenhas; Ron Kapusta; Michael C. W. Coln (IEEE J. Solid State Circuits, 2018)

A 12-Bit 31.1- $ mu$ W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance. - Junhua Shen; Akira Shikata; Anping Liu; Baozhen Chen; Frederick Chalifoux (IEEE J. Solid State Circuits, 2019)