Influence of wafer thinning process on backside damage in 3D integration. - Tadao Nakamura; Yoriko Mizushima; Hideki Kitada; Young-Suk Kim; Nobuhide Maeda; Shoichi Kodama; Ryuichi Sugie; Hiroshi Hashimoto; Akihito Kawai; Kazuhisa Arai; Akira Uedono; Takayuki Ohba (3DIC, 2013)

Advanced BEOL Materials, Processes, and Integration to Reduce Line Resistance of Damascene Cu, Co, and Subtractive Ru Interconnects. - Takeshi Nogami; Oleg Gluschenkov; Yasir Sulehria; Son Nguyen; Brown Peethala; Huai Huang; Hosadurga Shobha; Nick A. Lanzillo; Raghuveer Patlolla; Devika Sil; Andrew Simon; Daniel Edelstein; et al. (VLSI Technology and Circuits, 2022)

Impact of Cu Pad Density on Cu-CMP and Bonding Yield for Chip-to-Wafer Hybrid Bonding. - Mariappan Murugesan; Hiroyuki Hashimoto; Kentaro Mihara; Takashi Hare; Takafumi Fukushima; Fumihiro Inoue; Akira Uedono (3DIC, 2024)