Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding. - Edgar Holmann; Toyohiko Yoshida; Akira Yamada 005; Shin-ichi Uramoto (J. VLSI Signal Process., 1998)

A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor. - Atsushi Mohri; Akira Yamada 005; Y. Yoshida; Hisakazu Sato; Hidehiro Takata; K. Nakakimura; M. Hashizume; Y. Shimotsuma; K. Tsuchihashi (IEEE J. Solid State Circuits, 1999)

The D30V/MPEG multimedia processor. - Hidehiro Takata; Tetsuya Watanabe; Tetsuo Nakajima; Takashi Takagaki; Hisakazu Sato; Atsushi Mohri; Akira Yamada 005; Toshiki Kanamoto; Yoshio Matsuda; Shuhei Iwade; Yasutaka Horiba (IEEE Micro, 1999)