Development of Sprite Drawing Hardware Combining High-Level Synthesis and FPGA Internal Memory. - Keigo Aoki; Akira Yamawaki 003 (IECC, 2024)

Performance variation caused by sprite drawing pattern for high-level synthesized sprite drawing hardware. - Yuka Otani; Akira Yamawaki 003 (IECC, 2024)

Hardware Implementation of Calibration Data Loading in Device Driver for an SPI Peripheral. - Hibiki Shinozaki; Akira Yamawaki 003 (IECC, 2024)