Akira Yamawaki

According to our database1, Akira Yamawaki authored at least 29 papers between 2001 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2019
Effect of Parallel Processing by Duplicating Histogram in Automatic Image Binarization for High-Level Synthesis.
Proceedings of the 20th International Conference on Parallel and Distributed Computing, 2019

Development of Filled Circle Drawing in High-Level Synthesis Oriented Game Programming Library.
Proceedings of the 20th International Conference on Parallel and Distributed Computing, 2019

2018
A Describing Method of an Image Processing Software in C for a High-Level Synthesis Considering a Function Chaining.
IEICE Trans. Inf. Syst., 2018

Construction of Parallel Random I/O Codes Using Coset Coding with Hamming Codes.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Unrestricted-Rate Parallel Random Input-Output Codes for Multilevel Flash Memory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Describing Methods for High-level Synthesis of Histogram Generation and Their Evaluation.
Proceedings of the TENCON 2018, 2018

An Evaluation of Burst Transfer Inferred by a High-level Synthesis Tool.
Proceedings of the TENCON 2018, 2018

An Upper Bound on the Generalized Cayley Distance.
Proceedings of the International Symposium on Information Theory and Its Applications, 2018

2017
Worst-Case Performance of ILIFC with Inversion Cells.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Lower Bounds on the Number of Writing Operations by ILIFC with Inversion Cells.
CoRR, 2017

Construction of parallel RIO codes using coset coding with hamming codes.
Proceedings of the 2017 IEEE Information Theory Workshop, 2017

Lower bounds on the number of write operations by index-less indexed flash code with inversion cells.
Proceedings of the 2017 IEEE International Symposium on Information Theory, 2017

Construction of unrestricted-rate parallel random input-output code.
Proceedings of the 2017 IEEE International Symposium on Information Theory, 2017

2016
Maximization of average number of rewriting of ILIFC with inversion operation.
Proceedings of the 2016 International Symposium on Information Theory and Its Applications, 2016

Battery Life Estimation of Sensor Node with Zero Standby Power Consumption.
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

2015
Identify a Specified Fish Species by the Co-occurrence Matrix and AdaBoost.
Proceedings of the Software Engineering, 2015

2013
Underwater optical image dehazing using guided trigonometric bilateral filtering.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2010
An Efficient Hardware Architecture from C Program with Memory Access to Hardware.
Proceedings of the Computational Science and Its Applications, 2010

An Architecture of Prototyping System for Dynamic Partial Reconfiguration on FPGA.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2009
An intermediate hardware model with load/store unit for C to FPGA.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008
An FPGA implementation of a DWT with 5/3 filter using semi-programmable hardware.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip.
Proceedings of the 13th International Conference on Parallel and Distributed Systems, 2007

A Programmable Load/Store Unit on C-based Hardware Design for FPGA.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2005
Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor.
Proceedings of the 8th International Symposium on Parallel Architectures, 2005

An efficient parallel processing using a cache memory with synchronization on a Soc-multiprocessor.
Proceedings of the Third IASTED International Conference on Circuits, 2005

2004
Evaluation of mechanisms introduced to improve performance of TSVM cache.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2004

2002
Organization of Shared Memory with Synchronization for Multiprocessor-on-a-chip.
Proceedings of the 9th International Conference on Parallel and Distributed Systems, 2002

2001
Tagged communication and synchronization memory for multiprocessor-on-a-chip.
Systems and Computers in Japan, 2001


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