Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication. - Akitaka Hiratsuka; Akira Tsuchiya; Hidetoshi Onodera (MWSCAS, 2017)

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation. - Akitaka Hiratsuka; Akira Tsuchiya; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (A-SSCC, 2018)

A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. - Akira Tsuchiya; Akitaka Hiratsuka; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (SoCC, 2019)

Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity. - Akira Tsuchiya; Akitaka Hiratsuka; Toshiyuki Inoue; Keiji Kishine; Hidetoshi Onodera (IEICE Trans. Electron., 2019)

Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. - Akira Tsuchiya; Akitaka Hiratsuka; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (IEICE Trans. Electron., 2020)