Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS. - Fahim ur Rahman; Rajesh Pamula 001; Akshat Boora; Xun Sun; Visvesh Sathe 001 (ISSCC, 2019)

A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS. - Xun Sun; Akshat Boora; Wenbing Zhang; Venkata Rajesh Pamula 001; Visvesh Sathe 001 (ISSCC, 2019)

Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. - Xun Sun; Akshat Boora; Rajesh Pamula 001; Chi-Hsiang Huang 001; Diego Peña-Colaiocco; Visvesh S. Sathe 001 (VLSI Circuits, 2020)

UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. - Xun Sun; Akshat Boora; Rajesh Pamula 001; Chi-Hsiang Huang 001; Diego Peña-Colaiocco; Visvesh S. Sathe 001 (VLSI Circuits, 2020)