A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes. - Alaa Aldin Al Hariri; Fabrice Monteiro; Loïc Siéler; Abbas Dandache (IOLTS, 2013)

Configurable and high-throughput architectures for Quasi-cyclic low-density parity-check codes. - Alaa Aldin Al Hariri; Fabrice Monteiro; Loïc Siéler; Abbas Dandache (ICECS, 2014)

Architectures numériques configurables pour le traitement rapide sur FPGA de codes correcteurs d'erreurs de la famille QC-LDPC. (Configurable digital architectures for the fast processing on FPGA of error correcting codes from the QCLDPC family). - Alaa Aldin Al Hariri (2015)