Timestamp snooping: an approach for extending SMPs. - Milo M. K. Martin; Daniel J. Sorin; Anastassia Ailamaki; Alaa R. Alameldeen; Ross M. Dickson; Carl J. Mauer; Kevin E. Moore; Manoj Plakal; Mark D. Hill; David A. Wood 001 (ASPLOS, 2000)

Estimating the Selectivity of XML Path Expressions for Internet Scale Applications. - Ashraf Aboulnaga; Alaa R. Alameldeen; Jeffrey F. Naughton (VLDB, 2001)

Variability in Architectural Simulations of Multi-Threaded Workloads. - Alaa R. Alameldeen; David A. Wood 001 (HPCA, 2003)

Simulating a $2M Commercial Server on a $2K PC. - Alaa R. Alameldeen; Milo M. K. Martin; Carl J. Mauer; Kevin E. Moore; Min Xu; Mark D. Hill; David A. Wood 001; Daniel J. Sorin (Computer, 2003)

Addressing Workload Variability in Architectural Simulations. - Alaa R. Alameldeen; David A. Wood 001 (IEEE Micro, 2003)

Adaptive Cache Compression for High-Performance Processors. - Alaa R. Alameldeen; David A. Wood 001 (ISCA, 2004)

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. - Milo M. K. Martin; Daniel J. Sorin; Bradford M. Beckmann; Michael R. Marty; Min Xu; Alaa R. Alameldeen; Kevin E. Moore; Mark D. Hill; David A. Wood 001 (SIGARCH Comput. Archit. News, 2005)

IPC Considered Harmful for Multiprocessor Workloads. - Alaa R. Alameldeen; David A. Wood 001 (IEEE Micro, 2006)

Interactions Between Compression and Prefetching in Chip Multiprocessors. - Alaa R. Alameldeen; David A. Wood 001 (HPCA, 2007)

Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. - Keith A. Bowman; Alaa R. Alameldeen; Srikanth T. Srinivasan; Chris Wilkerson (ISLPED, 2007)

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. - Chris Wilkerson; Hongliang Gao; Alaa R. Alameldeen; Zeshan Chishti; Muhammad M. Khellah; Shih-Lien Lu (ISCA, 2008)

Improving cache lifetime reliability at ultra-low voltages. - Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Wei Wu 024; Shih-Lien Lu (MICRO, 2009)

Trading Off Cache Capacity for Low-Voltage Operation. - Chris Wilkerson; Hongliang Gao; Alaa R. Alameldeen; Zeshan Chishti; Muhammad M. Khellah; Shih-Lien Lu (IEEE Micro, 2009)

Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors. - Keith A. Bowman; Alaa R. Alameldeen; Srikanth T. Srinivasan; Chris Wilkerson (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Reducing cache power with low-cost, multi-bit error-correcting codes. - Chris Wilkerson; Alaa R. Alameldeen; Zeshan Chishti; Wei Wu 024; Dinesh Somasekhar; Shih-Lien Lu (ISCA, 2010)

Energy-efficient cache design using variable-strength error-correcting codes. - Alaa R. Alameldeen; Ilya Wagner; Zeshan Chishti; Wei Wu 024; Chris Wilkerson; Shih-Lien Lu (ISCA, 2011)

Guest Editor's Introduction. - Alaa R. Alameldeen (J. Instr. Level Parallelism, 2011)

Adaptive Cache Design to Enable Reliable Low-Voltage Operation. - Alaa R. Alameldeen; Zeshan Chishti; Chris Wilkerson; Wei Wu 024; Shih-Lien Lu (IEEE Trans. Computers, 2011)

Redundancy and ECC mechanisms to improve energy efficiency of on-die interconnects. - Amr Helmy; Alaa R. Alameldeen (ICEAC, 2012)

Improving multi-core performance using mixed-cell cache architecture. - Samira Manabi Khan; Alaa R. Alameldeen; Chris Wilkerson; Jaydeep Kulkarni; Daniel A. Jiménez (HPCA, 2013)

Improving DRAM performance by parallelizing refreshes with accesses. - Kevin Kai-Wei Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (HPCA, 2014)

Improving cache performance using read-write partitioning. - Samira Manabi Khan; Alaa R. Alameldeen; Chris Wilkerson; Onur Mutlu; Daniel A. Jiménez (HPCA, 2014)

Transparent Hardware Management of Stacked DRAM as Part of Memory. - Jaewoong Sim; Alaa R. Alameldeen; Zeshan Chishti; Chris Wilkerson; Hyesoon Kim (MICRO, 2014)

The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study. - Samira Manabi Khan; Donghyuk Lee; Yoongu Kim; Alaa R. Alameldeen; Chris Wilkerson; Onur Mutlu (SIGMETRICS, 2014)

Base-Victim Compression: An Opportunistic Cache Compression Architecture. - Jayesh Gaur; Alaa R. Alameldeen; Sreenivas Subramoney (ISCA, 2016)

Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses. - Kevin Kai-Wei Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (CoRR, 2016)

Probabilistic replacement strategies for improving the lifetimes of NVM-based caches. - Elizabeth Reed; Alaa R. Alameldeen; Helia Naeimi; Patrick Stolt (MEMSYS, 2017)

Detecting and mitigating data-dependent DRAM failures by exploiting current memory content. - Samira Manabi Khan; Chris Wilkerson; Zhe Wang 023; Alaa R. Alameldeen; Donghyuk Lee; Onur Mutlu (MICRO, 2017)

A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM. - Samira Manabi Khan; Chris Wilkerson; Donghyuk Lee; Alaa R. Alameldeen; Onur Mutlu (IEEE Comput. Archit. Lett., 2017)

Improving DRAM Performance by Parallelizing Refreshes with Accesses. - Kevin K. Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (CoRR, 2017)

Opportunistic compression for direct-mapped DRAM caches. - Alaa R. Alameldeen; Rajat Agarwal (MEMSYS, 2018)

Compresso: Pragmatic Main Memory Compression. - Esha Choukse; Mattan Erez; Alaa R. Alameldeen (MICRO, 2018)

CHAMELEON: A Dynamically Reconfigurable Heterogeneous Memory System. - Jagadish B. Kotra; Haibo Zhang 005; Alaa R. Alameldeen; Chris Wilkerson; Mahmut T. Kandemir (MICRO, 2018)

CompressPoints: An Evaluation Methodology for Compressed Memory Systems. - Esha Choukse; Mattan Erez; Alaa R. Alameldeen (IEEE Comput. Archit. Lett., 2018)

Reducing DRAM Refresh Overheads with Refresh-Access Parallelism. - Kevin K. Chang; Donghyuk Lee; Zeshan Chishti; Alaa R. Alameldeen; Chris Wilkerson; Yoongu Kim; Onur Mutlu (CoRR, 2018)

ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions. - Berkin Akin; Zeshan A. Chishti; Alaa R. Alameldeen (MICRO, 2019)

A Case For Asymmetric Processing in Memory. - Berkin Akin; Alaa R. Alameldeen (IEEE Comput. Archit. Lett., 2019)

Compact Leakage-Free Support for Integrity and Reliability. - Meysam Taassori; Rajeev Balasubramonian; Siddhartha Chhabra; Alaa R. Alameldeen; Manjula Peddireddy; Rajat Agarwal; Ryan Stutsman (ISCA, 2020)

SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads. - Abanti Basak; Jilan Lin; Ryan Lorica; Xinfeng Xie; Zeshan Chishti; Alaa R. Alameldeen; Yuan Xie 001 (ISPASS, 2020)

Speculative interference attacks: breaking invisible speculation schemes. - Mohammad Behnia; Prateek Sahu; Riccardo Paccagnella; Jiyong Yu; Zirui Neil Zhao; Xiang Zou; Thomas Unterluggauer; Josep Torrellas; Carlos V. Rozas; Adam Morrison 001; Frank McKeen; Fangfei Liu; et al. (ASPLOS, 2021)

Improving Streaming Graph Processing Performance using Input Knowledge. - Abanti Basak; Zheng Qu; Jilan Lin; Alaa R. Alameldeen; Zeshan Chishti; Yufei Ding 001; Yuan Xie 001 (MICRO, 2021)

Guest Editors' Introduction: Near-Memory and In-Memory Processing. - Hai Li 001; Alaa R. Alameldeen; Onur Mutlu (IEEE Des. Test, 2022)

Message from the MICRO 2024 Program Chairs. - Daniel A. Jiménez; Alaa R. Alameldeen (MICRO, 2024)

INTERFACE: An Indirect, Partitioned, Random, Fully-Associative Cache to Avoid Shared Last-Level Cache Attacks. - Yonas Kelemework; Alaa R. Alameldeen (SEED, 2024)

AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures. - Bo Fu; Leo Tenenbaum; David Adler; Assaf Klein; Arpit Gogia; Alaa R. Alameldeen; Marco Guarnieri; Mark Silberstein; Oleksii Oleksenko; Gururaj Saileshwar (ASPLOS (2), 2025)