Development of a prototype to detect speed limit violation for better traffic management. - Joyeeta Goswami; Shirsha Ghosh; Shivaditya Katiyar; Alak Majumder (IC3, 2015)

Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs. - Sandeep Kumar Singh 003; Abir J. Mondal; Alak Majumder (LATS, 2015)

LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder. - Pritam Bhattacharjee; Alak Majumder (iNIS, 2016)

A 90 nm leakage control transistor based clock gating for low power flip flop applications. - Pritam Bhattacharjee; Alak Majumder; Tushar Dhabal Das (MWSCAS, 2016)

A method to design a comparator for sampled data processing applications. - Rama Prasad Acharya; Abir J. Mondal; Alak Majumder (VDAT, 2016)

A constraint driven technique for MOS amplifier design. - Paromita Bhattacharjee; Abir J. Mondal; Alak Majumder (VDAT, 2016)

A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. - Monalisa Das; Alak Majumder; Abir J. Mondal; Bidyut K. Bhattacharyya (iNIS, 2017)

Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip. - Alak Majumder; Pritam Bhattacharjee (iNIS, 2017)

A Design Methodology for MOS Current Mode Logic VCO. - Abir J. Mondal; Alak Majumder; Bidyut K. Bhattacharyya (iNIS, 2017)

Binary Counter Based Gated Clock Tree for Integrated CPU Chip. - Bipasha Nath; Alak Majumder (iNIS, 2017)

Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment. - Shirsha Ghosh; Alak Majumder; Joyeeta Goswami; Abhishek Kumar; Saraju P. Mohanty; Bidyut K. Bhattacharyya (IEEE Consumer Electron. Mag., 2017)

Pay-Cloak: A Biometric Back Cover for Smartphones: Facilitating secure contactless payments and identity virtualization at low cost to end users. - Alak Majumder; Joyeeta Goswami; Shirsha Ghosh; Rishu Shrivastawa; Saraju P. Mohanty; Bidyut K. Bhattacharyya (IEEE Consumer Electron. Mag., 2017)

Reconstruction of a single square pulse originally having 40 ps width coming from a lossy and noisy channel in a point to point interconnect. - Alak Majumder; Bidyut K. Bhattacharyya (Turkish J. Electr. Eng. Comput. Sci., 2017)

Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect. - Alak Majumder; Abir J. Mondal; Bidyut K. Bhattacharyya (Integr., 2017)

A mathematical formulation to design and implementation of a low voltage swing transceiver circuit. - Abir J. Mondal; Alak Majumder; Bidyut K. Bhattacharyya (Integr., 2017)

Gated Clock Tree Circuit to Reduce the Noise in Silicon Chip. - Alak Majumder (J. Low Power Electron., 2017)

A 65 nm Design of 0.6 V/8.98 μW Process-Voltage-Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications. - Alak Majumder; Abir J. Mondal; Bidyut K. Bhattacharyya (J. Low Power Electron., 2017)

LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications. - Pritam Bhattacharjee; Bipasha Nath; Alak Majumder (CoRR, 2018)

Data-Dependent Clock Gating approach for Low Power Sequential System. - Dhiraj Sarkar; Pritam Bhattacharjee; Alak Majumder (CoRR, 2018)

A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%. - Nivedita Laskar; Suman Debnath; Alak Majumder; Bidyut K. Bhattacharyya (J. Circuits Syst. Comput., 2018)

A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips. - Alak Majumder; Pritam Bhattacharjee; Tushar Dhabal Das (J. Circuits Syst. Comput., 2018)

A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application. - Pritam Bhattacharjee; Alak Majumder (J. Circuits Syst. Comput., 2019)

Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication. - Alak Majumder; Monalisa Das; Suraj Kumar Saw; Abir J. Mondal; Bidyut K. Bhattacharyya (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Electro-optic Reversible Toffoli Gate with Optimal Count of LiNbO3 Mach-Zehnder Interferometers. - Shashank Awasthi; Saurav Sharma; Sanjeev Kumar Metya; Alak Majumder (NorCAS, 2020)

A 90nm PVT Tolerant Current Mode Frequency Divider with Wide Locking Range. - Madhusudan Maiti; Shubhro Chakrabartty; Alaaddin Al-Shidaifat; Hanjung Song; Bidyut K. Bhattacharyya; Alak Majumder (NorCAS, 2020)

Modelling and analysis of a hybrid CS-CMOS ring VCO with wide tuning range. - Madhusudan Maiti; Alak Majumder; Shubhro Chakrabartty; Hanjung Song; Bidyut K. Bhattacharyya (Microelectron. J., 2020)

A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time. - Pritam Bhattacharjee; Bidyut K. Bhattacharyya; Alak Majumder (Circuits Syst. Signal Process., 2021)

A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link. - Mithilesh Kumar 008; Alak Majumder; Abir J. Mondal; Arijit Raychowdhury; Bidyut K. Bhattacharyya (Integr., 2022)

Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current. - Mithilesh Kumar 008; Alak Majumder; Abir J. Mondal (J. Circuits Syst. Comput., 2022)

Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC. - Pritam Bhattacharjee; Prerna Rana; Bidyut K. Bhattacharyya; Alak Majumder (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Double Gate JLT Based New TIGFET for Dynamic C2MOS Application. - Tika Ram Pokhrel; Alak Majumder (APCCAS, 2023)

Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS. - Pritam Bhattacharjee; G. Naveen Goud; Vipin Kumar Singh 002; Vijay Pratap Yadav; Abir J. Mondal; Alak Majumder (RADIOELEKTRONIKA, 2023)

Ti:LiNbO3 Based EO-MZI Count Optimized Design of Reversible Peres Gate. - Barnali Chowdhury; Shashank Awasthi; Mohammad Arif Bin Jalil; Alak Majumder; Sanjeev Kumar Metya (RADIOELEKTRONIKA, 2023)

A variation resilient keeper design for high performance domino logic applications. - Jyoti Kandpal; Tika Ram Pokhrel; Shalu Saini; Alak Majumder (Integr., 2023)

Design of an Operational Transconductance Amplifier-Based Charge Pump for Phase-Locked Loop Applications. - Payali Das; Alak Majumder (iSES, 2024)

Exploring the Application of Variable Frequency Clock as the Constituent of OCT. - Priyanka J; Pritam Bhattacharjee; Alak Majumder (iSES, 2024)

An Algorithmic Approach of Generating a VFC of Low Average Frequency Ramp. - Priyanka J; Ankita Deb; Pritam Bhattacharjee; Alak Majumder (iSES, 2024)

A Method of Variable Frequency Clock Generation. - Vipin Kumar Singh 002; Vijay Pratap Yadav; Tika Ram Pokhrel; Pritam Bhattacharjee; Alak Majumder (iSES, 2024)

Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile. - Pritam Bhattacharjee; Alak Majumder (VLSID, 2024)

Enhancing intrusion detection using wireless sensor networks: A novel ahp-madm aggregated multiple type 3 fuzzy logic-based k-barriers prediction system. - Anirban Tarafdar; Azharuddin Sheikh; Pinki Majumder; Abhijit Baidya; Alak Majumder; Bidyut K. Bhattacharyya; Uttam Kumar Bera (Peer Peer Netw. Appl., 2024)

Time Domain and Area Efficient Smart Temperature Sensor Exploiting Channel Length Modulation Coefficient. - Kuntal Chakraborty; Alak Majumder; Abir J. Mondal (J. Circuits Syst. Comput., 2024)

A Multi-Resolution Mode Energy and Area Efficient All Digital Smart Temperature Sensor. - Kuntal Chakraborty; Alak Majumder; Abir J. Mondal (ICEIC, 2025)

Soft-Start Header Power Gating for Inrush Alleviated Current Profile. - Vijay Pratap Yadav; Vipin Kumar Singh 002; Tika Ram Pokhrel; Abir Jyoti Mandal; Sanjeev Kumar Metya; Alak Majumder (ICEIC, 2025)