An implementation of a state assignment heuristic. - Alan J. Coppola (DAC, 1986)

New Methods in the Analysis of Logic Minimization Data and Algorithms. - Alan J. Coppola (DAC, 1989)

Tokenized State Machine Model for Synthesis of Sequential Circuits into EPLDs and FPGAs. - Alan J. Coppola; Marek A. Perkowski; Robert Anderson; Jeffrey S. Freedman; Edmund Pierzchala (Synthesis for Control Dominated Circuits, 1992)

An Exact Solution to the Fitting Problem in the Application Specific State Machine Device. - Marek A. Perkowski; Malgorzata Chrzanowska-Jeske; Edmund Pierzchala; Alan J. Coppola (J. Circuits Syst. Comput., 1994)

Regular Realization of Symmetric Functions Using Reversible Logic. - Marek A. Perkowski; Malgorzata Chrzanowska-Jeske; Alan Mishchenko; Xiaoyu Song; Anas Al-Rabadi; Bart Massey; Pawel Kerntopf; Andrzej Buller; Lech Józwiak; Alan J. Coppola (DSD, 2001)

Board-level multiterminal net assignment. - Xiaoyu Song; William N. N. Hung; Alan Mishchenko; Malgorzata Chrzanowska-Jeske; Alan J. Coppola; Andrew A. Kennings (ACM Great Lakes Symposium on VLSI, 2002)

On segmented channel routability. - William N. N. Hung; Xiaoyu Song; Alan J. Coppola; Andrew A. Kennings (ISCAS (1), 2002)

Board-level multiterminal net assignment for the partial cross-bar architecture. - Xiaoyu Song; William N. N. Hung; Alan Mishchenko; Malgorzata Chrzanowska-Jeske; Andrew A. Kennings; Alan J. Coppola (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Segmented channel routability via satisfiability. - William N. N. Hung; Xiaoyu Song; El Mostapha Aboulhamid; Andrew A. Kennings; Alan J. Coppola (ACM Trans. Design Autom. Electr. Syst., 2004)

OpenFPGA CoreLib core library interoperability effort. - Michael J. Wirthlin; Daniel S. Poznanovic; P. Sundararajan; Alan J. Coppola; D. Pellerin; Walid A. Najjar; R. Bruce; M. Babst; O. Pritchard; Paolo Palazzari; Georgi Kuzmanov (Parallel Comput., 2008)