CGaAs PowerPC FXU. - Alan J. Drake; Todd D. Basso; Spencer M. Gold; Keith L. Kraver; Phiroze N. Parakh; Claude R. Gauthier; P. Sean Stetson; Richard B. Brown (DAC, 2000)

A microprocessor design project in an introductory VLSI course. - Richard B. Brown; Ronald J. Lomax; Gordon A. Carichner; Alan J. Drake (IEEE Trans. Educ., 2000)

Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications. - Seungbae Lee; Gi-Joon Nam; Junseok Chae; Hanseup Kim; Alan J. Drake (DAC, 2001)

Resonant clocking using distributed parasitic capacitance. - Alan J. Drake; Kevin J. Nowka; Tuyet Nguyen; Jeffrey L. Bums; Richard B. Brown (CICC, 2003)

Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI. - Alan J. Drake; Kevin J. Nowka; Richard B. Brown (VLSI-SOC, 2003)

Resonant clocking using distributed parasitic capacitance. - Alan J. Drake; Kevin J. Nowka; Tuyet Nguyen; Jeffrey L. Burns; Richard B. Brown (IEEE J. Solid State Circuits, 2004)

Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications. - Seungbae Lee; Gi-Joon Nam; Junseok Chae; Hanseup Kim; Alan J. Drake (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor. - Alan J. Drake; Robert M. Senger; Harmander Deogun; Gary D. Carpenter; Soraya Ghiasi; Tuyet Nguyen; Norman K. James; Michael S. Floyd; Vikas Pokala (ISSCC, 2007)

Adaptive energy management features of the POWER7TM processor. - Michael S. Floyd; Bishop Brock; Malcolm S. Ware; Karthick Rajamani; Alan J. Drake; Charles Lefurgy; Lorena Pesantez (Hot Chips Symposium, 2010)

Active management of timing guardband to save energy in POWER7. - Charles Lefurgy; Alan J. Drake; Michael S. Floyd; Malcolm Allen-Ware; Bishop Brock; José A. Tierno; John B. Carter (MICRO, 2011)

Introducing the Adaptive Energy Management Features of the Power7 Chip. - Michael S. Floyd; Malcolm Allen-Ware; Karthick Rajamani; Bishop Brock; Charles Lefurgy; Alan J. Drake; Lorena Pesantez; Tilman Gloekler; José A. Tierno; Pradip Bose; Alper Buyuktosunoglu (IEEE Micro, 2011)

Voltage droop reduction using throttling controlled by timing margin feedback. - Michael S. Floyd; Alan J. Drake; Robert W. Berry; Harold Chase; Richard L. Willaman; Jarom Peña (VLSIC, 2012)

Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor. - Alan J. Drake; Michael S. Floyd; Richard L. Willaman; Derek J. Hathaway; Joshua Hernandez; Crystal Soja; Marshall D. Tiner; Gary D. Carpenter; Robert M. Senger (ISLPED, 2013)

Innovative practices session 7C: Self-calibration & trimming. - Chen-Yong Cher; Yiorgos Makris; C. Thibeault; Alan J. Drake (VTS, 2013)

Runtime power reduction capability of the IBM POWER7+ chip. - Michael S. Floyd; Alan J. Drake; Nicole S. Schwartz; Robert W. Berry; Charles Lefurgy; Malcolm S. Ware; Karthick Rajamani; Victor V. Zyuban; Richard L. Willaman; Ruby M. Zgabay (IBM J. Res. Dev., 2013)

Active Guardband Management in Power7+ to Save Energy and Maintain Reliability. - Charles Lefurgy; Alan J. Drake; Michael S. Floyd; Malcolm Allen-Ware; Bishop Brock; José A. Tierno; John B. Carter; Robert W. Berry (IEEE Micro, 2013)

Optimization and modeling of resonant clocking inductors for the POWER8TM microprocessor. - Robert A. Groves; Phillip J. Restle; Alan J. Drake; David Shan; Michael G. R. Thomson (CICC, 2014)

5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor. - Phillip J. Restle; David Shan; David Hogenmiller; Yong Kim; Alan J. Drake; Jason Hibbeler; Thomas J. Bucelot; Gregory S. Still; Keith A. Jenkins; Joshua Friedrich (ISSCC, 2014)

Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths. - Xiaobin Yuan; Pawel Owczarczyk; Alan J. Drake; Marshall D. Tiner; David T. Hui; John P. Pennings; Francesco A. Campisano; Richard L. Willaman; Leana M. Cropp; Rudolph D. Dussault (IEEE Trans. Very Large Scale Integr. Syst., 2015)

36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Wei-Chih Chen; Wen-Hung Huang; Yu-Chi Chen; Yu-Jie Huang; Alan J. Drake; Chin-Hua Wen; Paul Ranucci; Hsin-Hung Kuo; Aidong Yin; et al. (ISSCC, 2025)