Implementation of a third-generation 1.1-GHz 64-bit microprocessor. - Georgios K. Konstadinidis; Kevin Normoyle; Samson Wong; Sutikshan Bhutani; Harry Stuimer; Timothy Johnson; Alan P. Smith 002; Daniel Y. Cheung; Fabrizio Romano; Shifeng Yu; Sung-Hun Oh; Victor Melamed; et al. (IEEE J. Solid State Circuits, 2002)

A 40nm 16-core 128-thread CMT SPARC SoC processor. - Jinuk Luke Shin; Kenway W. Tam; Dawei Huang; Bruce Petrick; Ha Pham; Changku Hwang; Hongping Penny Li; Alan P. Smith 002; Timothy Johnson; Francis Schumacher; David Greenhill; Ana Sonia Leon; et al. (ISSCC, 2010)

A 40 nm 16-Core 128-Thread SPARC SoC Processor. - Jinuk Luke Shin; Dawei Huang; Bruce Petrick; Changku Hwang; Kenway W. Tam; Alan P. Smith 002; Ha Pham; Hongping Penny Li; Timothy Johnson; Francis Schumacher; Ana Sonia Leon; Allan Strong (IEEE J. Solid State Circuits, 2011)

The next-generation 64b SPARC core in a T4 SoC processor. - Jinuk Luke Shin; Heechoul Park; Hongping Penny Li; Alan P. Smith 002; Youngmoon Choi; Harikaran Sathianathan; Sudesna Dash; Sebastian Turullols; Song Kim; Robert P. Masleid; Georgios K. Konstadinidis; Robert T. Golla; et al. (ISSCC, 2012)

The Next Generation 64b SPARC Core in a T4 SoC Processor. - Jinuk Luke Shin; Robert T. Golla; Hongping Penny Li; Sudesna Dash; Youngmoon Choi; Alan P. Smith 002; Harikaran Sathianathan; Mayur Joshi; Heechoul Park; Mohamed Elgebaly; Sebastian Turullols; Song Kim; et al. (IEEE J. Solid State Circuits, 2013)

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. - Georgios K. Konstadinidis; Hongping Penny Li; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; Vijay Srinivasan; et al. (IEEE J. Solid State Circuits, 2016)