Low Power Heuristic Block-level Voltage/Frequency Scheduling. - Li-Chuan Weng; Xiaojun Wang 001; Alan P. Su; Bin Liu 001 (ESA/VLSI, 2004)

Applying ESL in A Dual-Core SoC Platform Designing. - Alan P. Su; Robert Chen (SoCC, 2006)

An architectural co-synthesis algorithm for energy-aware network-on-chip design. - Wei-Hsuan Hung; Yi-Jung Chen; Chia-Lin Yang; Yen-Sheng Chang; Alan P. Su (SAC, 2007)

Flow Maximization for NoC Routing Algorithms. - Ying-Cherng Lan; Michael C. Chen; Alan P. Su; Yu Hen Hu; Sao-Jie Chen (ISVLSI, 2008)

Fluidity concept for NoC: A congestion avoidance and relief routing scheme. - Ying-Cherng Lan; Michael C. Chen; Alan P. Su; Yu Hen Hu; Sao-Jie Chen (SoCC, 2008)

Transaction Level Modeling and Design Space Exploration for SOC Test Architectures. - Chin-Yao Chang; Chih-Yuan Hsiao; Kuen-Jong Lee; Alan P. Su (Asian Test Symposium, 2009)

A low-cost SOC debug platform based on on-chip test architectures. - Kuen-Jong Lee; Si-Yuan Liang; Alan P. Su (SoCC, 2009)

Application of ESL synthesis on GSM edge algorithm for base station. - Alan P. Su (ASP-DAC, 2010)

A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example. - W. M. Young; Chua-Huang Huang; Alan P. Su; Chewnpu Jou; Fu-Lung Hsueh (ASP-DAC, 2010)

A software/hardware co-debug platform for multi-core systems. - Kuen-Jong Lee; Alan P. Su; Long-Feng Chen; Jia-Wei Jhou; Jiff Kuo; Mark Liu (ASICON, 2011)

Buffer size minimization method considering mix-clock domains and discontinuous data access. - Lih-Yih Chiou; Liang-Ying Lu; Bo-Chi Lin; Alan P. Su (APCCAS, 2012)

A low power synthesis flow for multi-rate systems. - Hsin-Pang Kuo; Alan P. Su; Kuen-Jong Lee (VLSI-DAT, 2017)

A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip. - Chun-Wei Wu; Kuen-Jong Lee; Alan P. Su (IEEE Trans. Computers, 2018)