Carbon nanotube transistor compact model for circuit design and performance optimization. - Jie Deng; Albert Lin 002; Gordon C. Wan; H.-S. Philip Wong (ACM J. Emerg. Technol. Comput. Syst., 2008)

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits. - Nishant Patil; Jie Deng; Albert Lin 002; H.-S. Philip Wong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. - Nishant Patil; Albert Lin 002; Jie Zhang 007; H.-S. Philip Wong; Subhasish Mitra (DAC, 2009)

Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. - Jie Zhang 007; Shashikanth Bobba; Nishant Patil; Albert Lin 002; H.-S. Philip Wong; Giovanni De Micheli; Subhasish Mitra (DAC, 2010)

Carbon nanotube circuits: Living with imperfections and variations. - Jie Zhang 007; Nishant Patil; Albert Lin 002; H.-S. Philip Wong; Subhasish Mitra (DATE, 2010)

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated. - Hai Wei; Jie Zhang 007; Lan Wei; Nishant Patil; Albert Lin 002; Max M. Shulaker; Hong-Yu Chen; H.-S. Philip Wong; Subhasish Mitra (ICCAD, 2011)

Carbon Nanotube Robust Digital VLSI. - Jie Zhang 007; Albert Lin 002; Nishant Patil; Hai Wei; Lan Wei; H.-S. Philip Wong; Subhasish Mitra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)