Cyclist: Accelerating hardware development. - Jonathan Bachrach; Albert Magyar; Daniel Palmer Dabbelt; Patrick Li; Richard Lin; Krste Asanovic (ICCAD, 2017)

Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations. - Adam M. Izraelevitz; Jack Koenig; Patrick Li; Richard Lin; Angie Wang; Albert Magyar; Donggyu Kim; Colin Schmidt 001; Chick Markley; Jim Lawson; Jonathan Bachrach (ICCAD, 2017)

Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes. - Albert Magyar; David Biancolin; John Koenig; Sanjit A. Seshia; Jonathan Bachrach; Krste Asanovic (ICCAD, 2019)

Invited: Chipyard - An Integrated SoC Research and Implementation Environment. - Alon Amid; David Biancolin; Abraham Gonzalez; Daniel Grubb; Sagar Karandikar; Harrison Liew; Albert Magyar; Howard Mao; Albert J. Ou; Nathan Pemberton; Paul Rigge; Colin Schmidt 001; et al. (DAC, 2020)

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs. - Alon Amid; David Biancolin; Abraham Gonzalez; Daniel Grubb; Sagar Karandikar; Harrison Liew; Albert Magyar; Howard Mao; Albert J. Ou; Nathan Pemberton; Paul Rigge; Colin Schmidt 001; et al. (IEEE Micro, 2020)

Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim. - David Biancolin; Albert Magyar; Sagar Karandikar; Alon Amid; Borivoje Nikolic; Jonathan Bachrach; Krste Asanovic (IEEE Micro, 2021)

Improving FPGA Simulation Capacity with Automatic Resource Multi-Threading - Albert Magyar (2021)