A parallelized way to provide data encryption and integrity checking on a processor-memory bus. - Reouven Elbaz; Lionel Torres; Gilles Sassatelli; Pierre Guillemin; Michel Bardouillet; Albert Martinez (DAC, 2006)

A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus. - Reouven Elbaz; Lionel Torres; Gilles Sassatelli; Pierre Guillemin; Michel Bardouillet; Albert Martinez (PATMOS, 2006)

Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems. - Reouven Elbaz; Lionel Torres; Gilles Sassatelli; Pierre Guillemin; Michel Bardouillet; Albert Martinez (ReCoSoC, 2006)

Block-Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor-Memory Transactions. - Reouven Elbaz; Lionel Torres; Gilles Sassatelli; Pierre Guillemin; Michel Bardouillet; Albert Martinez (Trans. Comput. Sci., 2010)