MIS: A Multiple-Level Logic Optimization System. - Robert K. Brayton; Richard L. Rudell; Alberto L. Sangiovanni-Vincentelli; Albert R. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Boolean decomposition in multi-level logic optimization. - Srinivas Devadas; Albert R. Wang; A. Richard Newton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1988)

Logic verification using binary decision diagrams in a logic synthesis environment. - Sharad Malik; Albert R. Wang; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1988)

Timing optimization of combinational logic. - Kanwar Jit Singh; Albert R. Wang; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1988)

Multi-level logic minimization using implicit don't cares. - Karen A. Bartlett; Robert K. Brayton; Gary D. Hachtel; Reily M. Jacoby; Christopher R. Morrison; Richard L. Rudell; Alberto L. Sangiovanni-Vincentelli; Albert R. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Multi-level Logic Simplification Using Don't Cares and Filters. - Alexander Saldanha; Albert R. Wang; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1989)

Boolean decomposition in multilevel logic optimization. - Srinivas Devadas; Albert R. Wang; A. Richard Newton; Alberto L. Sangiovanni-Vincentelli (IEEE J. Solid State Circuits, 1989)

Computation of floating mode delay in combinational circuits: practice and implementation. - Srinivas Devadas; Kurt Keutzer; Sharad Malik; Albert R. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Challenges in code generation for embedded processors. - Guido Araujo; Srinivas Devadas; Kurt Keutzer; Stan Y. Liao; Sharad Malik; Ashok Sudarsanam; Steven W. K. Tjiang; Albert R. Wang (Code Generation for Embedded Processors, 1994)

Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. - Srinivas Devadas; Kurt Keutzer; Sharad Malik; Albert R. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Certified timing verification and the transition delay of a logic circuit. - Srinivas Devadas; Kurt Keutzer; Sharad Malik; Albert R. Wang (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Verification of asynchronous interface circuits with bounded wire delays. - Srinivas Devadas; Kurt Keutzer; Sharad Malik; Albert R. Wang (J. VLSI Signal Process., 1994)

A Design and Validation System for Asynchronous Circuits. - Peter Vanbekbergen; Albert R. Wang; Kurt Keutzer (DAC, 1995)

Storage Assignment to Decrease Code Size. - Stan Y. Liao; Srinivas Devadas; Kurt Keutzer; Steven W. K. Tjiang; Albert R. Wang (ACM Trans. Program. Lang. Syst., 1996)

Code Optimization Techniques in Embedded DSP Microprocessors. - Stan Y. Liao; Srinivas Devadas; Kurt Keutzer; Steven W. K. Tjiang; Albert R. Wang (Des. Autom. Embed. Syst., 1998)

Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. - Ying Zhao; Sharad Malik; Albert R. Wang; Matthew W. Moskewicz; Conor F. Madigan (ICCD, 2001)