SYSDES: A Systolic Array Automation Design System. - PeiZong Lee; Albert Yang; Kee Yip; Jeffrey Wu (PP, 1989)

A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS. - Lan-Chou Cho; Hsiang-Hui Chang; Augusto Marques; Albert Yang; Chinq-Shiun Chiu; Guang-Kaai Dehng (A-SSCC, 2011)

Electric vehicle smart charging and vehicle-to-grid operation. - Siddhartha Mal; Arunabh Chattopadhyay; Albert Yang; Rajit Gadh (Int. J. Parallel Emergent Distributed Syst., 2013)

Causality Network of Infectious Disease Revealed With Causal Decomposition. - Jingpeng Sun; Kai Yuan; Chen Chen 036; Heng Xu; Hesong Wang; Yuxing Zhi; Silong Peng; Chung-Kang Peng; Norden E. Huang; Guangrui Huang; Albert Yang (IEEE J. Biomed. Health Informatics, 2023)