An 800-MHz embedded DRAM with a concurrent refresh mode. - Toshiaki Kirihata; Paul C. Parries; David R. Hanson; Hoki Kim; John Golz; Gregory Fredeman; Raj Rajeevakumar; John Griesemer; Norman Robson; Alberto Cestero; Babar A. Khan; Geng Wang; et al. (IEEE J. Solid State Circuits, 2005)

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips. - Norman Robson; John Safran; Chandrasekharan Kothandaraman; Alberto Cestero; Xiang Chen; Raj Rajeevakumar; Alan Leslie; Dan Moy; Toshiaki Kirihata; Subramanian S. Iyer (CICC, 2007)

Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM. - Daniel Fainstein; Sami Rosenblatt; Alberto Cestero; Norman Robson; Toshiaki Kirihata; Subramanian S. Iyer (VLSIC, 2012)

A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM. - Sami Rosenblatt; Srivatsan Chellappa; Alberto Cestero; Norman Robson; Toshiaki Kirihata; Subramanian S. Iyer (IEEE J. Solid State Circuits, 2013)

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM. - Sami Rosenblatt; Daniel Fainstein; Alberto Cestero; John Safran; Norman Robson; Toshiaki Kirihata; Subramanian S. Iyer (IEEE J. Solid State Circuits, 2013)

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. - Janakiraman Viraraghavan; Derek Leu; Balaji Jayaraman; Alberto Cestero; Robert Kilker; Ming Yin; John Golz; Rajesh Reddy Tummuru; Ramesh Raghavan; Dan Moy; Thejas Kempanna; Faraz Khan; et al. (VLSI Circuits, 2016)

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. - Gregory Fredeman; Donald W. Plass; Abraham Mathews; Janakiraman Viraraghavan; Kenneth Reyer; Thomas J. Knips; Thomas Miller; Elizabeth L. Gerhard; Dinesh Kannambadi; Chris Paone; Dongho Lee; Daniel Rainey 002; et al. (IEEE J. Solid State Circuits, 2016)

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity. - Balaji Jayaraman; Derek Leu; Janakiraman Viraraghavan; Alberto Cestero; Ming Yin; John Golz; Rajesh Reddy Tummuru; Ramesh Raghavan; Dan Moy; Thejas Kempanna; Faraz Khan; Toshiaki Kirihata; et al. (IEEE J. Solid State Circuits, 2018)

3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. - Rahul Mathur; Mudit Bhargava; Heath Perry; Alberto Cestero; Frank Frederick; Shawn Hung; Chien-Ju Chao; Daniel Smith; Daniel Fisher; Norman Robson; Xiaoqing Xu; Pranavi Chandupatla; et al. (CICC, 2021)