Low complexity iterative receivers for space-time block coded MC-CDMA downlink systems. - Alberto Jimenez-Pacheco; Mariano García Otero (EUSIPCO, 2005)

Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver. - Angel Fernandez Herrero; Alberto Jimenez-Pacheco; Gabriel Caffarena; Javier Casajús-Quirós (FPL, 2006)

Design and Implementation in FPGA of a MIMO Decoder for a 4G Wireless Receiver. - Alberto Jimenez-Pacheco; Angel Fernandez Herrero; Javier Casajús-Quirós (ICECS, 2006)

Turbo Multiuser Detection for MC-CDMA Downlink Systems with Transmit Diversity. - Alberto Jimenez-Pacheco (VTC Spring, 2007)

Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver. - Alberto Jimenez-Pacheco; Angel Fernandez Herrero; Francisco Javier Casajús-Quirós (VLSI Design, 2008)

A novel conflict-free memory and processor architecture for DVB-T2 LDPC decoding. - Alberto Jimenez-Pacheco; Onkar Dabeer (ICUMT, 2011)

Implementation of a wireless mesh network of ultra light MAVs with dynamic routing. - Alberto Jimenez-Pacheco; Denia Bouhired; Yannick Gasser; Jean-Christophe Zufferey; Dario Floreano; Bixio Rimoldi (GLOBECOM Workshops, 2012)