Low-power radix-4 divider. - Alberto Nannarelli; Tomás Lang (ISLPED, 1996)

Low-power radix-8 divider. - Alberto Nannarelli; Tomás Lang (ICCD, 1998)

Power-delay tradeoffs for radix-4 and radix-8 dividers. - Alberto Nannarelli; Tomás Lang (ISLPED, 1998)

Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16. - Alberto Nannarelli; Tomás Lang (IEEE Symposium on Computer Arithmetic, 1999)

Low-Power Radix-4 Combined Division and Square Root. - Alberto Nannarelli; Tomás Lang (ICCD, 1999)

Low-Power Divider. - Alberto Nannarelli; Tomás Lang (IEEE Trans. Computers, 1999)

Tradeoffs between residue number system and traditional FIR filters. - Alberto Nannarelli; Marco Re; Gian Carlo Cardarilli (ISCAS (2), 2001)

FPGA realization of RNS to binary signed conversion architecture. - Marco Re; Alberto Nannarelli; Gian Carlo Cardarilli; Roberto Lojacono (ISCAS (4), 2001)

Cached-code compression for energy minimization in embedded processors. - Luca Benini; Alberto Macii; Alberto Nannarelli (ISLPED, 2001)

Fast Radix-4 Retimed Division with Selection by Comparisons. - Elisardo Antelo; Tomás Lang; Paolo Montuschi; Alberto Nannarelli (ASAP, 2002)

Power characterization of digital filters implemented on FPGA. - Gian Carlo Cardarilli; Andrea Del Re; Alberto Nannarelli; Marco Re (ISCAS (5), 2002)

Power-delay tradeoffs in residue number system. - Alberto Nannarelli; Gian Carlo Cardarilli; Marco Re (ISCAS (5), 2003)

A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. - Andrea Del Re; Alberto Nannarelli; Marco Re (DATE, 2004)

Low-power implementation of polyphase filters in Quadratic Residue Number system. - Gian Carlo Cardarilli; Andrea Del Re; Alberto Nannarelli; Marco Re (ISCAS (2), 2004)

Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture. - Elisardo Antelo; Tomás Lang; Paolo Montuschi; Alberto Nannarelli (IEEE Symposium on Computer Arithmetic, 2005)

Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. - Gian Carlo Cardarilli; Andrea Del Re; Alberto Nannarelli; Marco Re (ISCAS (2), 2005)

Digit-Recurrence Dividers with Reduced Logical Depth. - Elisardo Antelo; Tomás Lang; Paolo Montuschi; Alberto Nannarelli (IEEE Trans. Computers, 2005)

Low-power adaptive filter based on RNS components. - G. L. Bernocchi; Gian Carlo Cardarilli; Andrea Del Re; Alberto Nannarelli; Marco Re (ISCAS, 2007)

A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture. - Tomás Lang; Alberto Nannarelli (IEEE Trans. Computers, 2007)

Power dissipation in division. - Wei Liu 016; Alberto Nannarelli (ACSCC, 2008)

Reducing power dissipation in pipelined accumulators. - Gian Carlo Cardarilli; Alberto Nannarelli; Marco Re (ACSCC, 2008)

Session TP8b1: Computer arithmetic II. - Alberto Nannarelli (ACSCC, 2008)

ADAPTO: full-adder based reconfigurable architecture for bit level operations. - Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re; Alberto Nannarelli (ISCAS, 2008)

A variant of a radix-10 combinational multiplier. - Luigi Dadda; Alberto Nannarelli (ISCAS, 2008)

On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters. - Gian Carlo Cardarilli; Alberto Nannarelli; Marco Re (VLSI-SoC (Selected Papers), 2008)

Division Unit for Binary Integer Decimals. - Tomás Lang; Alberto Nannarelli (ASAP, 2009)

On-chip Thermal Modeling Based on SPICE Simulation. - Wei Liu 016; Andrea Calimera; Alberto Nannarelli; Enrico Macii; Massimo Poncino (PATMOS, 2009)

Power dissipation challenges in multicore floating-point units. - Wei Liu 016; Alberto Nannarelli (ASAP, 2010)

Post-placement temperature reduction techniques. - Wei Liu 016; Alberto Nannarelli; Andrea Calimera; Enrico Macii; Massimo Poncino (DATE, 2010)

Radix-16 Combined Division and Square Root Unit. - Alberto Nannarelli (IEEE Symposium on Computer Arithmetic, 2011)

FPGA implementation of decimal processors for hardware acceleration. - Nicolas Borup; Jonas Dindorp; Alberto Nannarelli (NORCHIP, 2011)

Temperature dependent wire delay estimation in floorplanning. - Andreas Thor Winther; Wei Liu 016; Alberto Nannarelli; Sarma B. K. Vrudhula (NORCHIP, 2011)

FPGA Based Acceleration of Decimal Operations. - Alberto Nannarelli (ReConFig, 2011)

Imprecise arithmetic for low power image processing. - Pietro Albicocco; Gian Carlo Cardarilli; Alberto Nannarelli; Massimo Petricca; Marco Re (ACSCC, 2012)

Power efficient design of parallel/serial FIR filters in RNS. - Massimo Petricca; Pietro Albicocco; Gian Carlo Cardarilli; Alberto Nannarelli; Marco Re (ACSCC, 2012)

Design of power efficient FPGA based hardware accelerators for financial applications. - Jonas Stenbaek Hegner; Joakim Sindholt; Alberto Nannarelli (NORCHIP, 2012)

Comments on 'improving the speed of decimal division'. - Tomás Lang; Alberto Nannarelli (IET Comput. Digit. Tech., 2012)

Power Efficient Division and Square Root Unit. - Wei Liu 016; Alberto Nannarelli (IEEE Trans. Computers, 2012)

Truncated multipliers through power-gating for degrading precision arithmetic. - Pietro Albicocco; Gian Carlo Cardarilli; Alberto Nannarelli; Massimo Petricca; Marco Re (ACSSC, 2013)

Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. - Wei Liu 016; Andrea Calimera; Alberto Macii; Enrico Macii; Alberto Nannarelli; Massimo Poncino (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Twenty years of research on RNS for DSP: Lessons learned and future perspectives. - Pietro Albicocco; Gian Carlo Cardarilli; Alberto Nannarelli; Marco Re (ISIC, 2014)

Energy efficient FPGA based hardware accelerators for financial applications. - Jakob Kenn Toft; Alberto Nannarelli (NORCHIP, 2014)

Decimal engine for energy-efficient multicore processors. - Alberto Nannarelli (VLSI-SoC, 2014)

Guest Editors' Introduction: Special Section on Computer Arithmetic. - Alberto Nannarelli; Peter-Michael Seidel; Ping Tak Peter Tang (IEEE Trans. Computers, 2014)

A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration. - Gian Carlo Cardarilli; Leonardo Di Carlo; Alberto Nannarelli; Federico Maria Pandolfi; Marco Re (ISSPIT, 2015)

Characterization of RNS multiply-add units for power efficient DSP. - Gian Carlo Cardarilli; Alberto Nannarelli; Massimo Petricca; Marco Re (MWSCAS, 2015)

Thermal aware floorplanning incorporating temperature dependent wire delay estimation. - Andreas Thor Winther; Wei Liu 016; Alberto Nannarelli; Sarma B. K. Vrudhula (Microprocess. Microsystems, 2015)

Power and Thermal Efficient Numerical Processing. - Wei Liu 016; Alberto Nannarelli (Handbook on Data Centers, 2015)

Dynamically-loaded Hardware Libraries (HLL) technology for audio applications. - A. Esposito; Andrea Lomuscio; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ACSSC, 2016)

A hardware framework for on-chip FPGA acceleration. - Andrea Lomuscio; Gian Carlo Cardarilli; Alberto Nannarelli; Marco Re (ISIC, 2016)

Design and simulation of a quaternary memory cell based on a physical memristor. - Jonathan Taylor; Alberto Nannarelli (NORCAS, 2016)

Performance/Power Space Exploration for Binary64 Division Units. - Alberto Nannarelli (IEEE Trans. Computers, 2016)

A multi-format floating-point multiplier for power-efficient operations. - Alberto Nannarelli (SoCC, 2017)

Robust throughput boosting for low latency dynamic partial reconfiguration. - Alberto Nannarelli; Marco Re; Gian Carlo Cardarilli; Luca Di Nunzio; M. Spaziani Brunella; Rocco Fazzolari; F. Carbonari (SoCC, 2017)

Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. - Elisardo Antelo; Paolo Montuschi; Alberto Nannarelli (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Power Efficient Digital Front-End for Cognitive Radio Systems. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ACSSC, 2018)

Tunable Floating-Point for Energy Efficient Accelerators. - Alberto Nannarelli (ARITH, 2018)

Tunable Floating-Point for Artificial Neural Networks. - Marta Franceschi; Alberto Nannarelli; Maurizio Valle (ICECS, 2018)

Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Dario Gelfusa; Marco Matta; Alberto Nannarelli; Marco Re; Lorenzo Simone; Sergio Spanò (SMACD, 2018)

Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation. - Marta Franceschi; Alberto Nannarelli; Maurizio Valle (SMACD, 2018)

Approximated Canonical Signed Digit for Error Resilient Intelligent Computation. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ACSSC, 2019)

Digital Signal Processing Accelerator for RISC-V. - L. Calicchia; V. Ciotoli; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ICECS, 2019)

Fused Multiply-Add for Variable Precision Floating-Point. - Alberto Nannarelli (SoCC, 2019)

A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer. - Marco Matta; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Alberto Nannarelli; Marco Re; Sergio Spanò (IEEE Access, 2019)

An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm. - Sergio Spanò; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Alberto Nannarelli; Marco Re (IEEE Access, 2019)

Tunable Floating-Point Adder. - Alberto Nannarelli (IEEE Trans. Computers, 2019)

FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Alberto Nannarelli; Marco Re; Sergio Spanò (ACSSC, 2020)

Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors. - Alberto Nannarelli (ARITH, 2020)

N-Dimensional Approximation of Euclidean Distance. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

M-PSK Demodulator With Joint Carrier and Timing Recovery. - Daniele Giardino; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Special Section on "Emerging and Impacting Trends on Computer Arithmetic". - Mioara Joldes; Fabrizio Lamberti; Alberto Nannarelli (IEEE Trans. Emerg. Top. Comput., 2021)

Special Section on Scalable Computing for Blockchain Systems. - Hong-Ning Dai Senior; Zibin Zheng; Yan Zhang 002; Michael Rung-Tsong Lyu; Alberto Nannarelli (IEEE Trans. Emerg. Top. Comput., 2021)

Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Massimo Petricca; Marco Re (IEEE Trans. Emerg. Top. Comput., 2022)

Guest Editorial: Special Section on Emerging and Impacting Trends on Computer Arithmetic. - Stuart F. Oberman; Leonel Sousa; Bogdan Pasca 001; Alberto Nannarelli (IEEE Trans. Emerg. Top. Comput., 2022)

Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Riccardo La Cesa; Alberto Nannarelli; Marco Re (ACSSC, 2023)

An RNS-Based Initial Absolute Position Estimator for Electrical Encoders. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Re; Alberto Nannarelli; Sergio Spanò (IEEE Access, 2023)

Automatic Tunable Floating-Point Format Selection in a RISC-V Ecosystem. - Alberto Nannarelli; Marco Re; Gian Carlo Cardarilli; Luca Di Nunzio; Sergio Spanò (ApplePies, 2024)

Unified Digit Selection for Radix-4 Recurrence Division and Square Root. - David M. Harris; James E. Stine; Milos D. Ercegovac; Alberto Nannarelli; Katherine Parry; Cedar Turek (IEEE Trans. Computers, 2024)