System on chip with 1.12mW-32Gb/s AC-coupled 3D memory interface. - Roberto Canegallo; Luca Perugini; Alberto Pasini; Massimiliano Innocenti; Mauro Scandiuzzo; Roberto Guerrieri; Pier Luigi Rolandi (CICC, 2009)

RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip. - Fabio Campi; Ralf König 001; Michael Dreschmann; M. Neukirchner; Damien Picard; M. Jüttner; Eberhard Schüler; Antonio Deledda; Davide Rossi; Alberto Pasini; Michael Hübner 001; Jürgen Becker 001; et al. (SoC, 2009)