A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (Euro-Par, 2005)

An efficient cache design for scalable glueless shared-memory multiprocessors. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (Conf. Computing Frontiers, 2006)

Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (HiPC, 2007)

Scalable Directory Organization for Tiled CMP Architectures. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (CDES, 2008)

DiCo-CMP: Efficient cache coherency in tiled CMP architectures. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (IPDPS, 2008)

Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. - Alberto Ros 001; Ricardo Fernández-Pascual; Manuel E. Acacio; José M. García 001 (J. Parallel Distributed Comput., 2008)

Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (APPT, 2009)

Distance-aware round-robin mapping for large NUCA caches. - Alberto Ros 001; Marcelo Cintra; Manuel E. Acacio; José M. García 001 (HiPC, 2009)

Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs. - Alberto Ros 001; Manuel E. Acacio (Euro-Par Workshops, 2010)

EMC2: Extending Magny-Cours coherence for large-scale servers. - Alberto Ros 001; Blas Cuesta; Ricardo Fernández-Pascual; María Engracia Gómez; Manuel E. Acacio; Antonio Robles; José M. García 001; José Duato (HiPC, 2010)

A scalable organization for distributed directories. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (J. Syst. Archit., 2010)

A Direct Coherence Protocol for Many-Core Chip Multiprocessors. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (IEEE Trans. Parallel Distributed Syst., 2010)

Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation. - Antonio García-Guirado; Ricardo Fernández-Pascual; Alberto Ros 001; José M. García 001 (ICPP, 2011)

Self-related traces: An alternative to full-system simulation for NoCs. - Francisco Triviño; Francisco J. Andujar; Francisco J. Alfaro; José L. Sánchez 002; Alberto Ros 001 (HPCS, 2011)

Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks. - Blas Cuesta; Alberto Ros 001; María Engracia Gómez; Antonio Robles; José Duato (ISCA, 2011)

Complexity-effective multicore coherence. - Alberto Ros 001; Stefanos Kaxiras (PACT, 2012)

PS-Dir: a scalable two-level directory cache. - Joan J. Valls; Alberto Ros 001; Julio Sahuquillo; María Engracia Gómez; José Duato (PACT, 2012)

ASCIB: adaptive selection of cache indexing bits for removing conflict misses. - Alberto Ros 001; Polychronis Xekalakis; Marcelo Cintra; Manuel E. Acacio; José M. García 001 (ISLPED, 2012)

Cache Miss Characterization in Hierarchical Large-Scale Cache-Coherent Systems. - Alberto Ros 001; Blas Cuesta; María Engracia Gómez; Antonio Robles; José Duato (ISPA, 2012)

Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs. - Alberto Ros 001; Ricardo Fernández-Pascual; Manuel E. Acacio (SBAC-PAD, 2012)

Efficient, snoopless, System-on-Chip coherence. - Stefanos Kaxiras; Alberto Ros 001 (SoCC, 2012)

DAPSCO: Distance-aware partially shared cache organization. - Antonio García-Guirado; Ricardo Fernández-Pascual; Alberto Ros 001; José M. García 001 (ACM Trans. Archit. Code Optim., 2012)

Extending Magny-Cours Cache Coherence. - Alberto Ros 001; Blas Cuesta Saez; Ricardo Fernández-Pascual; María Engracia Gómez; Manuel E. Acacio; Antonio Robles; José M. García 001; José Duato (IEEE Trans. Computers, 2012)

Efficient Dir0B Cache Coherency for Many-Core CMPs. - José L. Abellán; Alberto Ros 001; Juan Fernández 001; Manuel E. Acacio (ICCS, 2013)

Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors. - Alberto Ros 001; Blas Cuesta; María Engracia Gómez; Antonio Robles; José Duato (ICPP, 2013)

A new perspective for efficient virtual-cache coherence. - Stefanos Kaxiras; Alberto Ros 001 (ISCA, 2013)

ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs. - José L. Abellán; Alberto Ros 001; Juan Fernández Peinador; Manuel E. Acacio (ICSAMOS, 2013)

Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks. - Blas Cuesta; Alberto Ros 001; María Engracia Gómez; Antonio Robles; José Duato (IEEE Trans. Computers, 2013)

Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (Euro-Par Workshops (2), 2014)

An Efficient, Self-Contained, On-chip Directory: DIR1-SISD. - Mahdad Davari; Alberto Ros 001; Erik Hagersten; Stefanos Kaxiras (PACT, 2015)

Early Experiences with Separate Caches for Private and Shared Data. - Juan M. Cebrian; Alberto Ros 001; Ricardo Fernández-Pascual; Manuel E. Acacio (e-Science, 2015)

Fast&Furious: A Tool for Detecting Covert Racing. - Alberto Ros 001; Stefanos Kaxiras (PARMA-DITAM@HiPEAC, 2015)

Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies. - Alberto Ros 001; Mahdad Davari; Stefanos Kaxiras (HPCA, 2015)

Turning Centralized Coherence and Distributed Critical-Section Execution on their Head: A New Approach for Scalable Distributed Shared Memory. - Stefanos Kaxiras; David Klaftenegger; Magnus Norgren; Alberto Ros 001; Konstantinos Sagonas (HPDC, 2015)

A Dual-Consistency Cache Coherence Protocol. - Alberto Ros 001; Alexandra Jimborean (IPDPS, 2015)

Callback: efficient synchronization without invalidation with a directory just for spin-waiting. - Alberto Ros 001; Stefanos Kaxiras (ISCA, 2015)

The Tag Filter Cache: An Energy-Efficient Approach. - Joan J. Valls; Julio Sahuquillo; Alberto Ros 001; María Engracia Gómez (PDP, 2015)

The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence. - Mahdad Davari; Alberto Ros 001; Erik Hagersten; Stefanos Kaxiras (ACM Trans. Archit. Code Optim., 2015)

Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses. - Alberto Ros 001; Polychronis Xekalakis; Marcelo Cintra; Manuel E. Acacio; José M. García 001 (IEEE Trans. Computers, 2015)

DASC-DIR: a low-overhead coherence directory for many-core processors. - Alberto Ros 001; Manuel E. Acacio (J. Supercomput., 2015)

PS-Cache: an energy-efficient cache design for chip multiprocessors. - Joan J. Valls; Alberto Ros 001; Julio Sahuquillo; María Engracia Gómez (J. Supercomput., 2015)

PS directory: a scalable multilevel directory cache for CMPs. - Joan J. Valls; Alberto Ros 001; Julio Sahuquillo; María Engracia Gómez (J. Supercomput., 2015)

POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics. - Alberto Ros 001; Carl Leonardsson; Christos Sakalis; Stefanos Kaxiras (PACT, 2016)

Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (ARCS, 2016)

Fencing Programs with Self-Invalidation and Self-Downgrade. - Parosh Aziz Abdulla; Mohamed Faouzi Atig; Stefanos Kaxiras; Carl Leonardsson; Alberto Ros 001; Yunyun Zhu (FORTE, 2016)

A Directory Cache with Dynamic Private-Shared Partitioning. - Joan J. Valls; María Engracia Gómez; Alberto Ros 001; Julio Sahuquillo (HiPC, 2016)

TokenTLB: A Token-Based Page Classification Approach. - Albert Esteve; Alberto Ros 001; Antonio Robles; María Engracia Gómez; José Duato (ICS, 2016)

Splash-3: A properly synchronized benchmark suite for contemporary research. - Christos Sakalis; Carl Leonardsson; Stefanos Kaxiras; Alberto Ros 001 (ISPASS, 2016)

Racer: TSO consistency via race detection. - Alberto Ros 001; Stefanos Kaxiras (MICRO, 2016)

Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead. - Konstantinos Koukos; Alberto Ros 001; Erik Hagersten; Stefanos Kaxiras (ACM Trans. Archit. Code Optim., 2016)

Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (J. Supercomput., 2016)

Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors. - Albert Esteve; Alberto Ros 001; María Engracia Gómez; Antonio Robles; José Duato (IEEE Trans. Parallel Distributed Syst., 2016)

A Hybrid Static-Dynamic Classification for Dual-Consistency Cache Coherence. - Alberto Ros 001; Alexandra Jimborean (IEEE Trans. Parallel Distributed Syst., 2016)

Automatic detection of extended data-race-free regions. - Alexandra Jimborean; Jonatan Waern; Per Ekemark; Stefanos Kaxiras; Alberto Ros 001 (CGO, 2017)

Way-combining directory: an adaptive and scalable low-cost coherence directory. - J. Rubén Titos Gil; Antonio Flores; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (ICS, 2017)

Non-Speculative Load-Load Reordering in TSO. - Alberto Ros 001; Trevor E. Carlson; Mehdi Alipour; Stefanos Kaxiras (ISCA, 2017)

A dedicated private-shared cache design for scalable multiprocessors. - Juan M. Cebrian; Ricardo Fernández-Pascual; Alexandra Jimborean; Manuel E. Acacio; Alberto Ros 001 (Concurr. Comput. Pract. Exp., 2017)

The Tag Filter Architecture: An energy-efficient cache and directory design. - Joan J. Valls; Alberto Ros 001; María Engracia Gómez; Julio Sahuquillo (J. Parallel Distributed Comput., 2017)

To be silent or not: on the impact of evictions of clean data in cache-coherent multicores. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (J. Supercomput., 2017)

TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs. - Albert Esteve; Alberto Ros 001; María Engracia Gómez; Antonio Robles; José Duato (IEEE Trans. Parallel Distributed Syst., 2017)

Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics. - Alberto Ros 001; Carl Leonardsson; Christos Sakalis; Stefanos Kaxiras (IEEE Trans. Parallel Distributed Syst., 2017)

Non-Speculative Store Coalescing in Total Store Order. - Alberto Ros 001; Stefanos Kaxiras (ISCA, 2018)

The Superfluous Load Queue. - Alberto Ros 001; Stefanos Kaxiras (MICRO, 2018)

Photonic-based express coherence notifications for many-core CMPs. - José L. Abellán; Eduardo Padierna; Alberto Ros 001; Manuel E. Acacio (J. Parallel Distributed Comput., 2018)

Mending Fences with Self-Invalidation and Self-Downgrade. - Parosh Aziz Abdulla; Mohamed Faouzi Atig; Stefanos Kaxiras; Carl Leonardsson; Alberto Ros 001; Yunyun Zhu (Log. Methods Comput. Sci., 2018)

Non-Speculative Load Reordering in Total Store Ordering. - Stefanos Kaxiras; Trevor E. Carlson; Mehdi Alipour; Alberto Ros 001 (IEEE Micro, 2018)

TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction. - Albert Esteve; Alberto Ros 001; Antonio Robles; María Engracia Gómez (IEEE Trans. Parallel Distributed Syst., 2018)

Automatic Detection of Large Extended Data-Race-Free Regions with Conflict Isolation. - Alexandra Jimborean; Per Ekemark; Jonatan Waern; Stefanos Kaxiras; Alberto Ros 001 (IEEE Trans. Parallel Distributed Syst., 2018)

Ghost loads: what is the cost of invisible speculation? - Christos Sakalis; Mehdi Alipour; Alberto Ros 001; Alexandra Jimborean; Stefanos Kaxiras; Magnus Själander (CF, 2019)

Filter caching for free: the untapped potential of the store-buffer. - Ricardo Alves 001; Alberto Ros 001; David Black-Schaffer; Stefanos Kaxiras (ISCA, 2019)

Efficient invisible speculative execution through selective delay and value prediction. - Christos Sakalis; Stefanos Kaxiras; Alberto Ros 001; Alexandra Jimborean; Magnus Själander (ISCA, 2019)

Way Combination for an Adaptive and Scalable Coherence Directory. - J. Rubén Titos Gil; Antonio Flores; Ricardo Fernández-Pascual; Alberto Ros 001; Salvador Petit; Julio Sahuquillo; Manuel E. Acacio (IEEE Trans. Parallel Distributed Syst., 2019)

Regional Out-of-Order Writes in Total Store Order. - Sawan Singh; Alexandra Jimborean; Alberto Ros 001 (PACT, 2020)

Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design. - Kim-Anh Tran; Christos Sakalis; Magnus Själander; Alberto Ros 001; Stefanos Kaxiras; Alexandra Jimborean (PACT, 2020)

Boosting Store Buffer Efficiency with Store-Prefetch Bursts. - Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (MICRO, 2020)

Speculative Enforcement of Store Atomicity. - Alberto Ros 001; Stefanos Kaxiras (MICRO, 2020)

TLB-based Block-Grain Classification of Private Data. - Bhargavi R. Upadhyay; Alberto Ros 001; Murty NS (PDP, 2020)

The Entangling Instruction Prefetcher. - Alberto Ros 001; Alexandra Jimborean (IEEE Comput. Archit. Lett., 2020)

PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. - J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (J. Parallel Distributed Comput., 2020)

Understanding Selective Delay as a Method for Efficient Secure Speculative Execution. - Christos Sakalis; Stefanos Kaxiras; Alberto Ros 001; Alexandra Jimborean; Magnus Själander (IEEE Trans. Computers, 2020)

Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. - J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (IEEE Trans. Parallel Distributed Syst., 2020)

TSOPER: Efficient Coherence-Based Strict Persistency. - Per Ekemark; Yuan Yao 009; Alberto Ros 001; Konstantinos Sagonas; Stefanos Kaxiras (HPCA, 2021)

A Cost-Effective Entangling Prefetcher for Instructions. - Alberto Ros 001; Alexandra Jimborean (ISCA, 2021)

Splash-4: Improving Scalability with Lock-Free Constructs. - Eduardo José Gómez-Hernández; Ruixiang Shao; Christos Sakalis; Stefanos Kaxiras; Alberto Ros 001 (ISPASS, 2021)

ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading. - Josué Feliu; Alberto Ros 001; Manuel E. Acacio; Stefanos Kaxiras (MICRO, 2021)

Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations. - Eduardo José Gómez-Hernández; Juan M. Cebrian; J. Rubén Titos Gil; Stefanos Kaxiras; Alberto Ros 001 (MICRO, 2021)

Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation. - Christos Sakalis; Zamshed I. Chowdhury; Shayne Wadle; Ismail Akturk; Alberto Ros 001; Magnus Själander; Stefanos Kaxiras; Ulya R. Karpuzcu (SEED, 2021)

On Value Recomputation to Accelerate Invisible Speculation. - Christos Sakalis; Zamshed I. Chowdhury; Shayne Wadle; Ismail Akturk; Alberto Ros 001; Magnus Själander; Stefanos Kaxiras; Ulya R. Karpuzcu (CoRR, 2021)

Efficient classification of private memory blocks. - Bhargavi R. Upadhyay; Alberto Ros 001; Jalpa Shah (J. Parallel Distributed Comput., 2021)

Composite Instruction Prefetching. - Gino Chacon; Elba Garza; Alexandra Jimborean; Alberto Ros 001; Paul V. Gratz; Daniel A. Jiménez; Samira Mirbagher Ajorpaz (ICCD, 2022)

Splash-4: A Modern Benchmark Suite with Lock-Free Constructs. - Eduardo José Gómez-Hernández; Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (IISWC, 2022)

Free atomics: hardware atomic operations without fences. - Ashkan Asgharzadeh; Juan M. Cebrian; Arthur Perais; Stefanos Kaxiras; Alberto Ros 001 (ISCA, 2022)

Berti: an Accurate Local-Delta Data Prefetcher. - Agustín Navarro-Torres; Biswabandan Panda; Jesús Alastruey-Benedé; Pablo Ibáñez 001; Víctor Viñals Yúfera; Alberto Ros 001 (MICRO, 2022)

Exploring Instruction Fusion Opportunities in General Purpose Processors. - Sawan Singh; Arthur Perais; Alexandra Jimborean; Alberto Ros 001 (MICRO, 2022)

Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (PDP, 2022)

Analysing software prefetching opportunities in hardware transactional memory. - Marina Shimchenko; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Manuel E. Acacio; Stefanos Kaxiras; Alberto Ros 001; Alexandra Jimborean (J. Supercomput., 2022)

Compiler-Assisted Compaction/Restoration of SIMD Instructions. - Juan M. Cebrian; Thibaud Balem; Adrián Barredo; Marc Casas; Miquel Moretó; Alberto Ros 001; Alexandra Jimborean (IEEE Trans. Parallel Distributed Syst., 2022)

DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. - J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (IEEE Trans. Parallel Distributed Syst., 2022)

CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions. - Sawan Singh; Josué Feliu; Manuel E. Acacio; Alexandra Jimborean; Alberto Ros 001 (PACT, 2023)

Rebasing Microarchitectural Research with Industry Traces. - Josué Feliu; Arthur Perais; Daniel A. Jiménez; Alberto Ros 001 (IISWC, 2023)

MBPlib: Modular Branch Prediction Library. - Emilio Domínguez-Sánchez; Alberto Ros 001 (ISPASS, 2023)

Fine-grain data classification to filter token coherence traffic. - Bhargavi R. Upadhyay; Alberto Ros 001; Supriya M (J. Parallel Distributed Comput., 2023)

Speculative inter-thread store-to-load forwarding in SMT architectures. - Josué Feliu; Alberto Ros 001; Manuel E. Acacio; Stefanos Kaxiras (J. Parallel Distributed Comput., 2023)

Bounding Speculative Execution of Atomic Regions to a Single Retry. - Eduardo José Gómez-Hernández; Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (ASPLOS (4), 2024)

Effective Context-Sensitive Memory Dependence Prediction. - Sebastian S. Kim; Alberto Ros 001 (HPCA, 2024)

Hardware Cache Locking for All Memory Updates. - Ashkan Asgharzadeh; Eduardo José Gómez-Hernández; Juan M. Cebrian; Stefanos Kaxiras; Alberto Ros 001 (ICCD, 2024)

Enhanced System-Level Coherence for Heterogeneous Unified Memory Architectures. - Anoop Mysore Nataraja; Ricardo Fernández-Pascual; Alberto Ros 001 (IISWC, 2024)

Alternate Path μ-op Cache Prefetching. - Sawan Singh; Arthur Perais; Alexandra Jimborean; Alberto Ros 001 (ISCA, 2024)

Temporarily Unauthorized Stores: Write First, Ask for Permission Later. - Juan M. Cebrian; Magnus Jahre; Alberto Ros 001 (MICRO, 2024)

Secure Prefetching for Secure Cache Systems. - Sumon Nath; Agustín Navarro-Torres; Alberto Ros 001; Biswabandan Panda (MICRO, 2024)

Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory. - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Manuel E. Acacio; Alberto Ros 001 (MICRO, 2024)

A First Exploration of Fine-Grain Coherence for Integrity Metadata. - Per Ekemark; Alberto Ros 001; Konstantinos Sagonas; Stefanos Kaxiras (SEED, 2024)

Flexible Swapping for the Cloud. - Milan Pandurov; Lukas Humbel; Dmitry Sepp; Adamos Ttofari; Leon Thomm; Do Le Quoc; Siddharth Chandrasekaran; Sharan Santhanam; Chuan Ye; Shai Bergman; Wei Wang; Sven Lundgren; et al. (CoRR, 2024)

On the interactions between ILP and TLP with hardware transactional memory. - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (Microprocess. Microsystems, 2024)

Wrong-Path-Aware Entangling Instruction Prefetcher. - Alberto Ros 001; Alexandra Jimborean (IEEE Trans. Computers, 2024)

No Rush in Executing Atomic Instructions. - Ashkan Asgharzadeh; Josué Feliu; Manuel E. Acacio; Stefanos Kaxiras; Alberto Ros 001 (HPCA, 2025)

Mascot: Predicting Memory Dependencies and Opportunities for Speculative Memory Bypassing. - Karl H. Mose; Sebastian S. Kim; Alberto Ros 001; Timothy M. Jones 001; Robert D. Mullins (HPCA, 2025)

Correct Wrong Path. - Bhargav Reddy Godala; Sankara Prasad Ramesh; Krishnam Tibrewala; Chrysanthos Pepi; Gino Chacon; Svilen Kanev; Gilles A. Pokam; Alberto Ros 001; Daniel A. Jiménez; Paul V. Gratz; David I. August (IEEE Comput. Archit. Lett., 2025)

WoperTM: Got Nacks? Use Them! - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Manuel E. Acacio; Alberto Ros 001 (IEEE Comput. Archit. Lett., 2025)

A Complexity-Effective Local Delta Prefetcher. - Agustín Navarro-Torres; Biswabandan Panda; Jesús Alastruey-Benedé; Pablo Ibáñez 001; Víctor Viñals Yúfera; Alberto Ros 001 (IEEE Trans. Computers, 2025)