Error masking in self-testable circuits. - Albrecht P. Stroele; Hans-Joachim Wunderlich (ITC, 1990)

Signature Analysis and Test Scheduling for Self-Testable Circuits. - Albrecht P. Stroele; Hans-Joachim Wunderlich (FTCS, 1991)

TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control. - Albrecht P. Ströle; Hans-Joachim Wunderlich (IEEE J. Solid State Circuits, 1991)

Self-Test Scheduling with Bounded Test Execution. - Albrecht P. Stroele (ITC, 1992)

Testablaufplanung und Testauswertung für selbsttestbare Schaltungen. - Albrecht P. Ströle (VDI-Verlag, 1992)

Partitioning and hierarchical description of self-testable designs. - Albrecht P. Stroele (VLSI, 1993)

Signature Analysis for Sequential Circuits with Reset. - Albrecht P. Stroele (EDAC-ETC-EUROASIC, 1994)

Configuring Flip-Flops to BIST Registers. - Albrecht P. Stroele; Hans-Joachim Wunderlich (ITC, 1994)

A unified approach to the extraction of realistic multiple bridging and break faults. - Gerald Spiegel; Albrecht P. Stroele (EURO-DAC, 1995)

Test register insertion with minimum hardware cost. - Albrecht P. Stroele; Hans-Joachim Wunderlich (ICCAD, 1995)

A Self-Test Approach Using Accumulators as Test Pattern Generators. - Albrecht P. Stroele (ISCAS, 1995)

Signature analysis and aliasing for sequential circuits. - Albrecht P. Stroele (VTS, 1995)

Arithmetic Pattern Generators for Built-In Self-Test. - Albrecht P. Stroele (ICCD, 1996)

Test response compaction using arithmetic functions. - Albrecht P. Stroele (VTS, 1996)

Methods to reduce test application time for accumulator-based self-test. - Albrecht P. Stroele; Frank Mayer (VTS, 1997)

BIST Pattern Generators Using Addition and Subtraction Operations. - Albrecht P. Stroele (J. Electron. Test., 1997)

Entwurf selbsttestbarer Schaltungen. - Albrecht P. Ströle (Teubner, 1998)

Configuring Arithmetic Pattern Generators and Response Compactors from the RT-Modules of a Circuit. - Frank Mayer; Albrecht P. Stroele (Asian Test Symposium, 1998)

Embedded self-testing checkers for low-cost arithmetic codes. - Steffen Tarnick; Albrecht P. Stroele (ITC, 1998)

Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions. - Albrecht P. Stroele (VTS, 1998)

Hardware-optimal test register insertion. - Albrecht P. Stroele; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults. - Gerald Spiegel; Albrecht P. Stroele (VLSI Design, 1998)

Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators. - Albrecht P. Stroele; Frank Mayer (Asian Test Symposium, 1999)

Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code. - Albrecht P. Stroele; Steffen Tarnick (VTS, 1999)

Signature Analysis for Test Responses of Sequential Circuits. - Albrecht P. Stroele (VLSI Design, 1999)

Synthesizing data paths with arithmetic self-test. - Albrecht P. Stroele (ISCAS, 2000)

A Versatile BIST Technique Combining Test Registers and Accumulators. - Frank Mayer; Albrecht P. Stroele (VLSI Design, 2000)

Synthesis for Arithmetic Built-In Self-Tes. - Albrecht P. Stroele (VTS, 2000)

Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes. - Albrecht P. Stroele; Steffen Tarnick (J. Electron. Test., 2000)

Scheduling tests for low power built-in self-test. - Tobias Schüle; Albrecht P. Stroele (ISCAS (5), 2001)

Test Scheduling for Minimal Energy Consumption under Power Constraints. - Tobias Schüle; Albrecht P. Stroele (VTS, 2001)