Compact Signed-Digit Adder Using Multiple-Valued Logic. - Alejandro F. González; Pinaki Mazumder (ARVLSI, 1997)

Circuit Design using Resonant Tunneling Diodes. - Pinaki Mazumder; Shriram Kulkarni; Mayukh Bhattacharya; Alejandro F. González (VLSI Design, 1998)

Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices. - Alejandro F. González; Pinaki Mazumder (IEEE Trans. Computers, 1998)

A prototyping technique for large-scale RTD-CMOS circuits. - Mayukh Bhattacharya; Shriram Kulkarni; Alejandro F. González; Pinaki Mazumder (ISCAS, 2000)

Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices. - Alejandro F. González; Mayukh Bhattacharya; Shriram Kulkarni; Pinaki Mazumder (ISMVL, 2000)

Redundant arithmetic, algorithms and implementations. - Alejandro F. González; Pinaki Mazumder (Integr., 2000)

A 250-MHz, 32-bit quantum MOS correlator prototype. - Shriram Kulkarni; Mayukh Bhattacharya; Alejandro F. González; Pinaki Mazumder (ICECS, 2001)

CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices. - Alejandro F. González; Mayukh Bhattacharya; Shriram Kulkarni; Pinaki Mazumder (IEEE J. Solid State Circuits, 2001)

Comparison of Bistable Circuits Based on Resonant-Tunneling Diodes. - Alejandro F. González; Pinaki Mazumder (VLSI Design, 2003)

A spatio-temporal access method based on snapshots and events. - Gilberto A. Gutiérrez; Gonzalo Navarro 001; M. Andrea Rodríguez; Alejandro F. González; José Orellana (GIS, 2005)