Available task-level parallelism on the Cell BE. - Alejandro Rico; Alex Ramírez; Mateo Valero (Sci. Program., 2009)

Performance and power evaluation of an in-line accelerator. - Alejandro Rico; Jeff H. Derby; Robert K. Montoye; Timothy H. Heil; Chen-Yong Cher; Pradip Bose (Conf. Computing Frontiers, 2010)

Comparing last-level cache designs for CMP architectures. - Augusto Vega; Alejandro Rico; Felipe Cabarcas; Alex Ramírez; Mateo Valero (IFMT, 2010)

Task Superscalar: An Out-of-Order Task Pipeline. - Yoav Etsion; Felipe Cabarcas; Alejandro Rico; Alex Ramírez; Rosa M. Badia; Eduard Ayguadé; Jesús Labarta; Mateo Valero (MICRO, 2010)

Interleaving granularity on high bandwidth memory architecture for CMPs. - Felipe Cabarcas; Alejandro Rico; Yoav Etsion; Alex Ramírez (ICSAMOS, 2010)

Trace-driven simulation of multithreaded applications. - Alejandro Rico; Alejandro Duran; Felipe Cabarcas; Yoav Etsion; Alex Ramírez; Mateo Valero (ISPASS, 2011)

On the simulation of large-scale architectures using multiple application abstraction levels. - Alejandro Rico; Felipe Cabarcas; Carlos Villavieja; Milan Pavlovic; Augusto Vega; Yoav Etsion; Alex Ramírez; Mateo Valero (ACM Trans. Archit. Code Optim., 2012)

Experiences with mobile processors for energy efficient HPC. - Nikola Rajovic; Alejandro Rico; James Vipond; Isaac Gelado; Nikola Puzovic; Alex Ramírez (DATE, 2013)

Trace filtering of multithreaded applications for CMP memory simulation. - Alejandro Rico; Alex Ramírez; Mateo Valero (ISPASS, 2013)

Raising the level of abstraction: simulation of large chip multiprocessors running multithreaded applications. - Alejandro Rico Carro (2013)

Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors. - Thomas Grass; Alejandro Rico; Marc Casas; Miquel Moretó; Alex Ramírez (Euro-Par Workshops (2), 2014)

Tibidabo: Making the case for an ARM-based HPC system. - Nikola Rajovic; Alejandro Rico; Nikola Puzovic; Chris Adeniyi-Jones; Alex Ramírez (Future Gener. Comput. Syst., 2014)

Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures. - Kallia Chronaki; Alejandro Rico; Rosa M. Badia; Eduard Ayguadé; Jesús Labarta; Mateo Valero (ICS, 2015)

Experiences in speeding up computer vision applications on mobile computing platforms. - Luna Backes; Alejandro Rico; Björn Franke (SAMOS, 2015)

POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware. - Kallia Chronaki; Miquel Moretó; Marc Casas; Alejandro Rico; Rosa M. Badia; Eduard Ayguadé; Jesús Labarta; Mateo Valero (PACT, 2016)

Evaluating the effect of last-level cache sharing on integrated GPU-CPU systems with heterogeneous applications. - Victor Garcia; Juan Gómez-Luna; Thomas Grass; Alejandro Rico; Eduard Ayguadé; Antonio J. Peña (IISWC, 2016)

Rebalancing the core front-end through HPC code analysis. - Ugljesa Milic; Paul M. Carpenter; Alejandro Rico; Alex Ramírez (IISWC, 2016)

TaskPoint: Sampled simulation of task-based programs. - Thomas Grass; Alejandro Rico; Marc Casas; Miquel Moretó; Eduard Ayguadé (ISPASS, 2016)

MUSA: a multi-level simulation approach for next-generation HPC machines. - Thomas Grass; César Allande; Adrià Armejach; Alejandro Rico; Eduard Ayguadé; Jesús Labarta; Mateo Valero; Marc Casas; Miquel Moretó (SC, 2016)

The mont-blanc prototype: an alternative approach for HPC systems. - Nikola Rajovic; Alejandro Rico; Filippo Mantovani; Daniel Ruiz 003; Josep Oriol Vilarrubi; Constantino Gómez; Luna Backes; Diego Nieto; Harald Servat; Xavier Martorell; Jesús Labarta; Eduard Ayguadé; et al. (SC, 2016)

ARM HPC Ecosystem and the Reemergence of Vectors: Invited Paper. - Alejandro Rico; José A. Joao; Chris Adeniyi-Jones; Eric Van Hensbergen (Conf. Computing Frontiers, 2017)

Sharing the instruction cache among lean cores on an asymmetric CMP for HPC applications. - Ugljesa Milic; Alejandro Rico; Paul M. Carpenter; Alex Ramírez (ISPASS, 2017)

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors. - Victor Garcia; Alejandro Rico; Carlos Villavieja; Paul M. Carpenter; Nacho Navarro; Alex Ramírez (Int. J. Parallel Program., 2017)

The ARM Scalable Vector Extension. - Nigel Stephens; Stuart Biles; Matthias Boettcher; Jacob Eapen; Mbou Eyole; Giacomo Gabrielli; Matt Horsnell; Grigorios Magklis; Alejandro Martinez; Nathanaël Prémillieu; Alastair Reid 001; Alejandro Rico; et al. (IEEE Micro, 2017)

Task Scheduling Techniques for Asymmetric Multi-Core Systems. - Kallia Chronaki; Alejandro Rico; Marc Casas; Miquel Moretó; Rosa M. Badia; Eduard Ayguadé; Jesús Labarta; Mateo Valero (IEEE Trans. Parallel Distributed Syst., 2017)

Scaling up performance of fat nodes for HPC. - Alejandro Rico (CF, 2019)

Cache Line Sharing and Communication in ECP Proxy Applications. - Joshua Randall 001; Alejandro Rico; José A. Joao (IWOMP, 2019)

On the Benefits of Tasking with OpenMP. - Alejandro Rico; Isaac Sánchez Barrera; José A. Joao; Joshua Randall 001; Marc Casas; Miquel Moretó (IWOMP, 2019)

DynaSprint: Microarchitectural Sprints with Dynamic Utility and Thermal Management. - Ziqiang Huang; José A. Joao; Alejandro Rico; Andrew D. Hilton; Benjamin C. Lee (MICRO, 2019)

On the maturity of parallel applications for asymmetric multi-core processors. - Kallia Chronaki; Miquel Moretó; Marc Casas; Alejandro Rico; Rosa M. Badia; Eduard Ayguadé; Mateo Valero (J. Parallel Distributed Comput., 2019)

Sampled Simulation of Task-Based Programs. - Thomas Grass; Trevor E. Carlson; Alejandro Rico; Germán Ceballos; Eduard Ayguadé; Marc Casas; Miquel Moretó (IEEE Trans. Computers, 2019)

Towards Data-Flow Parallelization for Adaptive Mesh Refinement Applications. - Kevin Sala; Alejandro Rico; Vicenç Beltran 001 (CLUSTER, 2020)

Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture. - Lingjun Zhu; Tuan Ta; Rossana Liu; Rahul Mathur; Xiaoqing Xu; Shidhartha Das; Ankit Kaul; Alejandro Rico; Doug Joseph; Brian Cline; Sung Kyu Lim (ISLPED, 2021)

System technology co-optimization and design challenges for 3D IC. - Supreet Jeloka; Brian Cline; Shidhartha Das; Benoit Labbe; Alejandro Rico; Rainer Herberholz; Javier A. DeLaCruz; Rahul Mathur; Shawn Hung (CICC, 2022)

DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations. - Víctor Soria Pardos; Adrià Armejach; Tiago Mück; Darío Suárez Gracia; José A. Joao; Alejandro Rico; Miquel Moretó (ISCA, 2023)

AMD XDNA NPU in Ryzen AI Processors. - Alejandro Rico; Satyaprakash Pareek; Javier Cabezas; David Clarke; Baris Özgül; Francisco Barat; Yao Fu; Stephan Münz; Dylan Stuart; Patrick Schlangen; Pedro Duarte; Sneha Date; et al. (IEEE Micro, 2024)