A 16bit 50kHz 177dB-FOMS Calibration-Free Bootstrapping-Free SC Delta-Sigma Modulator IP Block for Low-Power High-Resolution ADCs. - Alejandro Suanes; Michele Dei; Lluís Terés; Francisco Serra-Graells (DCIS, 2020)

A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation. - Alejandro Suanes; Lluís Terés; Michele Dei; Francisco Serra-Graells (ISCAS, 2021)

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. - Guillem Cabo; Gerard Candón; Xavier Carril; Max Doblas; Marc Domínguez; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2022)

A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs. - Alejandro Suanes; Michele Dei; Lluís Terés; Francisco Serra-Graells (Integr., 2022)

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. - Max Doblas; Gerard Candón; Xavier Carril; Marc Domínguez; Enric Erra; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2023)