An hybrid eDRAM/SRAM macrocell to implement first-level data caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Vicente Lorente; Ramon Canal; Pedro López 001; José Duato (MICRO, 2009)

Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (PACT, 2011)

MRU-Tour-based Replacement Algorithms for Last-Level Caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (SBAC-PAD, 2011)

Analyzing the optimal ratio of SRAM banks in hybrid caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (ICCD, 2012)

Combining recency of information with selective random and a victim cache in last-level caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (ACM Trans. Archit. Code Optim., 2012)

Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches. - Alejandro Valero; Salvador Petit; Julio Sahuquillo; Pedro López 001; José Duato (IEEE Trans. Computers, 2012)

Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. - Alejandro Valero; Julio Sahuquillo; Vicente Lorente; Salvador Petit; Pedro López 001; José Duato (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. - Vicente Lorente; Alejandro Valero; Julio Sahuquillo; Salvador Petit; Ramon Canal; Pedro López 001; José Duato (DATE, 2013)

Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity. - Vicente Lorente; Alejandro Valero; Ramon Canal (Euro-Par Workshops, 2013)

Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; José Duato (ICS, 2013)

Hybrid caches: design and data management. - Alejandro Valero (2013)

Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches. - Vicente Lorente; Alejandro Valero; Salvador Petit; Pierfrancesco Foglia; Julio Sahuquillo (HPCC/CSS/ICESS, 2014)

A reuse-based refresh policy for energy-aware eDRAM caches. - Alejandro Valero; Salvador Petit; Julio Sahuquillo; David R. Kaeli; José Duato (Microprocess. Microsystems, 2015)

Design of Hybrid Second-Level Caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (IEEE Trans. Computers, 2015)

Enhancing the L1 Data Cache Design to Mitigate HCI. - Alejandro Valero; Negar Miralaei; Salvador Petit; Julio Sahuquillo; Timothy M. Jones 001 (IEEE Comput. Archit. Lett., 2016)

Exploiting Data Compression to Mitigate Aging in GPU Register Files. - Francisco Candel; Alejandro Valero; Salvador Petit; Darío Suárez Gracia; Julio Sahuquillo (SBAC-PAD, 2017)

On Microarchitectural Mechanisms for Cache Wearout Reduction. - Alejandro Valero; Negar Miralaei; Salvador Petit; Julio Sahuquillo; Timothy M. Jones 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache. - Francisco Candel; Salvador Petit; Alejandro Valero; Julio Sahuquillo (Euro-Par, 2018)

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. - Alejandro Valero; Darío Suárez Gracia; Ruben Gran Tejero; Luis M. Ramos; Agustín Navarro-Torres; Adolfo Muñoz 001; Joaquín Ezpeleta; José Luis Briz; Ana C. Murillo; Eduardo Montijano; Javier Resano; María Villarroya-Gaudó; et al. (WCAE@ISCA, 2019)

Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance. - Francisco Candel; Alejandro Valero; Salvador Petit; Julio Sahuquillo (IEEE Trans. Computers, 2019)

An Aging-Aware GPU Register File Design Based on Data Redundancy. - Alejandro Valero; Francisco Candel; Darío Suárez Gracia; Salvador Petit; Julio Sahuquillo (IEEE Trans. Computers, 2019)

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files. - Alejandro Valero; Darío Suárez Gracia; Ruben Gran Tejero (IEEE Access, 2020)

RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU. - Yamilka Toca-Díaz; Alejandro Valero; Ruben Gran Tejero; Darío Suárez Gracia (CoRR, 2021)

A learning experience toward the understanding of abstraction-level interactions in parallel applications. - Alejandro Valero; Ruben Gran Tejero; Darío Suárez Gracia; Emanuel A. Georgescu; Joaquín Ezpeleta; Pedro Álvarez 001; Adolfo Muñoz 001; Luis M. Ramos; Pablo Ibáñez 001 (J. Parallel Distributed Comput., 2021)

peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter. - Darío Suárez Gracia; Alejandro Valero; Ruben Gran Tejero; María Villarroya-Gaudó; Víctor Viñals (DCIS, 2022)

Fast-track cache: a huge racetrack memory L1 data cache. - Hugo Tárrega; Alejandro Valero; Vicente Lorente; Salvador Petit; Julio Sahuquillo (ICS, 2022)

Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators. - Nicolás Landeros Muñoz; Alejandro Valero; Ruben Gran Tejero; Davide Zoni (J. Syst. Archit., 2022)

On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators. - Yamilka Toca-Díaz; Nicolás Landeros Muñoz; Ruben Gran Tejero; Alejandro Valero (DSD, 2023)

Ensuring the Accuracy of CNN Accelerators Supplied at Ultra-Low Voltage. - Yamilka Toca-Díaz; Ruben Gran Tejero; Alejandro Valero (ICCD, 2024)

Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators. - Yamilka Toca-Díaz; Ruben Gran Tejero; Alejandro Valero (J. Syst. Archit., 2024)

Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage. - Yamilka Toca-Díaz; Reynier Hernández Palacios; Ruben Gran Tejero; Alejandro Valero (Microprocess. Microsystems, 2024)

Dual Fast-Track Cache: Organizing Ring-Shaped Racetracks to Work as L1 Caches. - Alejandro Valero; Vicente Lorente; Salvador Petit; Julio Sahuquillo (IEEE Trans. Computers, 2025)