A New State Assignment Method Targeting FPGA Implementations. - Lech Józwiak; Aleksander Slusarczyk (EUROMICRO, 2000)

Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis. - Lech Józwiak; Artur Chojnacki; Aleksander Slusarczyk (DSD, 2001)

Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. - Aleksander Slusarczyk; Lech Józwiak (ISQED, 2002)

Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits. - Lech Józwiak; Aleksander Slusarczyk; Marek A. Perkowski (VLSI Design, 2002)

Fast and compact sequential circuits for the FPGA-based reconfigurable systems. - Lech Józwiak; Aleksander Slusarczyk; Artur Chojnacki (J. Syst. Archit., 2003)

An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods. - Lech Józwiak; Dominik Gawlowski; Aleksander Slusarczyk (DSD, 2004)

General decomposition of incompletely specified sequential machines with multi-state behavior realization. - Lech Józwiak; Aleksander Slusarczyk (J. Syst. Archit., 2004)

Multi-objective Optimal FSM State Assignment. - Lech Józwiak; Aleksander Slusarczyk; Dominik Gawlowski (DSD, 2006)

Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems. - Lech Józwiak; Dominik Gawlowski; Aleksander Slusarczyk (ICSAMOS, 2006)

High-Quality Circuit Synthesis for Modern Technologies. - Lech Józwiak; Artur Chojnacki; Aleksander Slusarczyk (ISQED, 2008)