IRQ Coloring: Mitigating Interrupt-Generated Interference on ARM Multicore Platforms. - Diogo Costa; Luca Cuomo; Daniel Oliveira 003; Ida Maria Savino; Bruno Morelli; José Martins; Fabrizio Tronci; Alessandro Biasci; Sandro Pinto 001 (NG-RES@HiPEAC, 2023)

Virtualized DDS Communication for Multi-Domain Systems: Architecture and Performance Evaluation of Design Alternatives. - Andrea Stevanato; Alessandro Biondi 001; Alessandro Biasci; Bruno Morelli (RTAS, 2023)

IRQ Coloring and the Subtle Art of Mitigating Interrupt-Generated Interference. - Diogo Costa; Luca Cuomo; Daniel Oliveira 003; Ida Maria Savino; Bruno Morelli; José Martins; Alessandro Biasci; Sandro Pinto 001 (RTCSA, 2023)

Supporting logical execution time in multi-core POSIX systems. - Davide Bellassai; Alessandro Biondi 001; Alessandro Biasci; Bruno Morelli (J. Syst. Archit., 2023)

RT-Mimalloc: A New Look at Dynamic Memory Allocation for Real-Time Systems. - Raffaele Giannessi; Alessandro Biondi 001; Alessandro Biasci (RTAS, 2024)

Learning Memory-Contention Timing Models With Automated Platform Profiling. - Andrea Stevanato; Matteo Zini; Alessandro Biondi 001; Bruno Morelli; Alessandro Biasci (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Taking a closer look at memory interference effects in commercial-off-the-shelf multicore SoCs. - Lorenzo Carletti; Andrea Serafini; Gianluca Brilli; Alessandro Capotondi; Alessandro Biasci; Paolo Valente; Andrea Marongiu (J. Syst. Archit., 2025)

Synchronous VS asynchronous reconfiguration of Memory Bandwidth Management Schemes: A comparative analysis. - Andrea Serafini; Alessandro Biasci; Bruno Morelli; Paolo Valente; Andrea Marongiu (J. Syst. Archit., 2025)