Optimal Design for Reservation Servers under Shared Resources. - Alessandro Biondi 001; Alessandra Melani; Marko Bertogna; Giorgio C. Buttazzo (ECRTS, 2014)

Exact Interference of Adaptive Variable-Rate Tasks under Fixed-Priority Scheduling. - Alessandro Biondi 001; Alessandra Melani; Mauro Marinoni; Marco Di Natale; Giorgio C. Buttazzo (ECRTS, 2014)

Hard Constant Bandwidth Server: Comprehensive formulation and critical scenarios. - Alessandro Biondi 001; Alessandra Melani; Marko Bertogna (SIES, 2014)

Engine control: task modeling and analysis. - Alessandro Biondi 001; Giorgio C. Buttazzo (DATE, 2015)

Supporting Component-Based Development in Partitioned Multiprocessor Real-Time Systems. - Alessandro Biondi 001; Giorgio C. Buttazzo; Marko Bertogna (ECRTS, 2015)

Feasibility Analysis of Engine Control Tasks under EDF Scheduling. - Alessandro Biondi 001; Giorgio C. Buttazzo; Stefano Simoncelli (ECRTS, 2015)

Response-time analysis for real-time tasks in engine control applications. - Alessandro Biondi 001; Marco Di Natale; Giorgio C. Buttazzo (ICCPS, 2015)

Dual-protocol support for Bluetooth LE devices. - Mauro Marinoni; Gianluca Franchino; Daniel Cesarini; Alessandro Biondi 001; Pasquale Buonocunto; Giorgio C. Buttazzo (INDIN, 2015)

Resource reservation for real-time self-suspending tasks: theory and practice. - Alessandro Biondi 001; Alessio Balsini; Mauro Marinoni (RTNS, 2015)

Response time analysis for G-EDF and G-DM scheduling of sporadic DAG-tasks with arbitrary deadline. - Andrea Parri; Alessandro Biondi 001; Mauro Marinoni (RTNS, 2015)

Real-time analysis of engine control applications with speed estimation. - Alessandro Biondi 001; Giorgio C. Buttazzo (DATE, 2016)

Lightweight Real-Time Synchronization under P-EDF on Symmetric and Asymmetric Multiprocessors. - Alessandro Biondi 001; Björn B. Brandenburg (ECRTS, 2016)

Performance-Driven Design of Engine Control Tasks. - Alessandro Biondi 001; Marco Di Natale; Giorgio C. Buttazzo (ICCPS, 2016)

OSEK-Like Kernel Support for Engine Control Applications under EDF Scheduling. - Vincenzo Apuzzo; Alessandro Biondi 001; Giorgio C. Buttazzo (RTAS, 2016)

Partitioning and Interface Synthesis in Hierarchical Multiprocessor Real-Time Systems. - Alessandro Biondi 001; Giorgio C. Buttazzo; Marko Bertogna (RTNS, 2016)

A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs. - Alessandro Biondi 001; Alessio Balsini; Marco Pagani; Enrico Rossi; Mauro Marinoni; Giorgio C. Buttazzo (RTSS, 2016)

A Blocking Bound for Nested FIFO Spin Locks. - Alessandro Biondi 001; Björn B. Brandenburg; Alexander Wieder (RTSS, 2016)

ARTE: arduino real-time extension for programming multitasking applications. - Pasquale Buonocunto; Alessandro Biondi 001; Marco Pagani; Mauro Marinoni; Giorgio C. Buttazzo (SAC, 2016)

Schedulability Analysis of Hierarchical Real-Time Systems under Shared Resources. - Alessandro Biondi 001; Giorgio C. Buttazzo; Marko Bertogna (IEEE Trans. Computers, 2016)

Timing-aware FPGA partitioning for real-time applications under dynamic partial reconfiguration. - Alessandro Biondi 001; Giorgio C. Buttazzo (AHS, 2017)

Semi-Partitioned Scheduling of Dynamic Real-Time Workload: A Practical Approach Based on Analysis-Driven Load Balancing. - Daniel Casini; Alessandro Biondi 001; Giorgio C. Buttazzo (ECRTS, 2017)

Constant bandwidth servers with constrained deadlines. - Daniel Casini; Luca Abeni; Alessandro Biondi 001; Tommaso Cucinotta; Giorgio C. Buttazzo (RTNS, 2017)

A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration. - Marco Pagani; Alessio Balsini; Alessandro Biondi 001; Mauro Marinoni; Giorgio C. Buttazzo (SoCC, 2017)

Real-Time Analysis and Design of a Dual Protocol Support for Bluetooth LE Devices. - Mauro Marinoni; Alessandro Biondi 001; Pasquale Buonocunto; Gianluca Franchino; Daniel Cesarini; Giorgio C. Buttazzo (IEEE Trans. Ind. Informatics, 2017)

Beyond the Weakly Hard Model: Measuring the Performance Cost of Deadline Misses. - Paolo Pazzaglia; Luigi Pannocchi; Alessandro Biondi 001; Marco Di Natale (ECRTS, 2018)

Reconciling security with virtualization: A dual-hypervisor design for ARM TrustZone. - Giorgiomaria Cicero; Alessandro Biondi 001; Giorgio C. Buttazzo; Anup Patel (ICIT, 2018)

Supporting temporal and spatial isolation in a hypervisor for ARM multicore platforms. - Paolo Modica; Alessandro Biondi 001; Giorgio C. Buttazzo; Anup Patel (ICIT, 2018)

Achieving Predictable Multicore Execution of Automotive Applications Using the LET Paradigm. - Alessandro Biondi 001; Marco Di Natale (RTAS, 2018)

Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures. - Daniel Casini; Alessandro Biondi 001; Geoffrey Nelissen; Giorgio C. Buttazzo (RTSS, 2018)

Partitioned Fixed-Priority Scheduling of Parallel Tasks Without Preemptions. - Daniel Casini; Alessandro Biondi 001; Geoffrey Nelissen; Giorgio C. Buttazzo (RTSS, 2018)

The SRP Resource Sharing Protocol for Self-Suspending Tasks. - Geoffrey Nelissen; Alessandro Biondi 001 (RTSS, 2018)

Beyond the Weakly Hard Model: Measuring the Performance Cost of Deadline Misses (Artifact). - Paolo Pazzaglia; Luigi Pannocchi; Alessandro Biondi 001; Marco Di Natale (Dagstuhl Artifacts Ser., 2018)

A survey of schedulability analysis techniques for rate-dependent tasks. - Timo Feld; Alessandro Biondi 001; Robert I. Davis 001; Giorgio C. Buttazzo; Frank Slomka (J. Syst. Softw., 2018)

A design flow for supporting component-based software development in multiprocessor real-time systems. - Alessandro Biondi 001; Giorgio C. Buttazzo; Marko Bertogna (Real Time Syst., 2018)

On the ineffectiveness of 1/m-based interference bounds in the analysis of global EDF and FIFO scheduling. - Alessandro Biondi 001; Youcheng Sun (Real Time Syst., 2018)

Response-Time Analysis of Engine Control Applications Under Fixed-Priority Scheduling. - Alessandro Biondi 001; Marco Di Natale; Giorgio C. Buttazzo (IEEE Trans. Computers, 2018)

Selecting the Transition Speeds of Engine Control Tasks to Optimize the Performance. - Alessandro Biondi 001; Marco Di Natale; Giorgio C. Buttazzo; Paolo Pazzaglia (ACM Trans. Cyber Phys. Syst., 2018)

Modeling and Analysis of Engine Control Tasks Under Dynamic Priority Scheduling. - Alessandro Biondi 001; Giorgio C. Buttazzo (IEEE Trans. Ind. Informatics, 2018)

Analyzing Parallel Real-Time Tasks Implemented with Thread Pools. - Daniel Casini; Alessandro Biondi 001; Giorgio C. Buttazzo (DAC, 2019)

Simple and General Methods for Fixed-Priority Schedulability in Optimization Problems. - Paolo Pazzaglia; Alessandro Biondi 001; Marco Di Natale (DATE, 2019)

A Bandwidth Reservation Mechanism for AXI-Based Hardware Accelerators on FPGAs. - Marco Pagani; Enrico Rossi; Alessandro Biondi 001; Mauro Marinoni; Giuseppe Lipari; Giorgio C. Buttazzo (ECRTS, 2019)

Analyses and architectures for mixed-critical systems: industry trends and research perspective. - Lars Bauer; Marvin Damschen; Dirk Ziegenbein; Arne Hamann 001; Alessandro Biondi 001; Giorgio C. Buttazzo; Jörg Henkel (EMSOFT Companion, 2019)

Towards the Hypervision of Hardware-based Control Flow Integrity for Arm Platforms. - Giulia Ferri; Giorgiomaria Cicero; Alessandro Biondi 001; Giorgio C. Buttazzo (ITASEC, 2019)

Optimizing the Functional Deployment on Multicore Platforms with Logical Execution Time. - Paolo Pazzaglia; Alessandro Biondi 001; Marco Di Natale (RTSS, 2019)

Hierarchical scheduling of real-time tasks over Linux-based virtual machines. - Luca Abeni; Alessandro Biondi 001; Enrico Bini (J. Syst. Softw., 2019)

Handling Transients of Dynamic Real-Time Workload Under EDF Scheduling. - Daniel Casini; Alessandro Biondi 001; Giorgio C. Buttazzo (IEEE Trans. Computers, 2019)

Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs. - Francesco Restuccia 002; Marco Pagani; Alessandro Biondi 001; Mauro Marinoni; Giorgio C. Buttazzo (ACM Trans. Embed. Comput. Syst., 2019)

FLORA: FLoorplan Optimizer for Reconfigurable Areas in FPGAs. - Biruk B. Seyoum; Alessandro Biondi 001; Giorgio C. Buttazzo (ACM Trans. Embed. Comput. Syst., 2019)

Predictable Memory-CPU Co-Scheduling with Support for Latency-Sensitive Tasks. - Daniel Casini; Paolo Pazzaglia; Alessandro Biondi 001; Marco Di Natale; Giorgio C. Buttazzo (DAC, 2020)

AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC. - Francesco Restuccia 002; Alessandro Biondi 001; Mauro Marinoni; Giorgiomaria Cicero; Giorgio C. Buttazzo (DAC, 2020)

Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs. - Francesco Restuccia 002; Marco Pagani; Alessandro Biondi 001; Mauro Marinoni; Giorgio C. Buttazzo (ECRTS, 2020)

Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC. - Francesco Restuccia 002; Alessandro Biondi 001; Mauro Marinoni; Giorgio C. Buttazzo (FCCM, 2020)

The AMPERE Project: : A Model-driven development framework for highly Parallel and EneRgy-Efficient computation supporting multi-criteria optimization. - Eduardo Quiñones; Sara Royuela; Claudio Scordino; Paolo Gai; Luís Miguel Pinho; Luís Nogueira; Jan Rollo; Tommaso Cucinotta; Alessandro Biondi 001; Arne Hamann 001; Dirk Ziegenbein; Hadi Saoud; et al. (ISORC, 2020)

A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling. - Daniel Casini; Alessandro Biondi 001; Geoffrey Nelissen; Giorgio C. Buttazzo (RTAS, 2020)

Integrating Online Safety-related Memory Tests in Multicore Real-Time Systems. - Ciro Donnarumma; Alessandro Biondi 001; Francesco De Rosa; Stefano Di Carlo (RTSS, 2020)

Front Matter, Table of Contents, Preface, Conference Organization. - Alessandro Vittorio Papadopoulos; Alessandro Biondi 001 (Dagstuhl Artifacts Ser., 2020)

Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact). - Francesco Restuccia 002; Marco Pagani; Alessandro Biondi 001; Mauro Marinoni; Giorgio C. Buttazzo (Dagstuhl Artifacts Ser., 2020)

A Safe, Secure, and Predictable Software Architecture for Deep Learning in Safety-Critical Systems. - Alessandro Biondi 001; Federico Nesti; Giorgiomaria Cicero; Daniel Casini; Giorgio C. Buttazzo (IEEE Embed. Syst. Lett., 2020)

Timing isolation and improved scheduling of deep neural networks for real-time systems. - Daniel Casini; Alessandro Biondi 001; Giorgio C. Buttazzo (Softw. Pract. Exp., 2020)

X-BaD: A Flexible Tool for Explanation-Based Bias Detection. - Marco Pacini; Federico Nesti; Alessandro Biondi 001; Giorgio C. Buttazzo (CSR, 2021)

Optimal Memory Allocation and Scheduling for DMA Data Transfers under the LET Paradigm. - Paolo Pazzaglia; Daniel Casini; Alessandro Biondi 001; Marco Di Natale (DAC, 2021)

Scheduling Replica Voting in Fixed-Priority Real-Time Systems. - Pietro Fara; Gabriele Serra; Alessandro Biondi 001; Ciro Donnarumma (ECRTS, 2021)

Event-Driven Delay-Induced Tasks: Model, Analysis, and Applications. - Federico Aromolo; Alessandro Biondi 001; Geoffrey Nelissen; Giorgio C. Buttazzo (RTAS, 2021)

Latency Analysis of I/O Virtualization Techniques in Hypervisor-Based Real-Time Systems. - Daniel Casini; Alessandro Biondi 001; Giorgiomaria Cicero; Giorgio C. Buttazzo (RTAS, 2021)

A Multi-Domain Software Architecture for Safe and Secure Autonomous Driving. - Luca Belluardo; Andrea Stevanato; Daniel Casini; Giorgiomaria Cicero; Alessandro Biondi 001; Giorgio C. Buttazzo (RTCSA, 2021)

Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms. - Francesco Restuccia 002; Alessandro Biondi 001 (RTSS, 2021)

Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC. - Biruk B. Seyoum; Marco Pagani; Alessandro Biondi 001; Giorgio C. Buttazzo (SAC, 2021)

SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms. - Alessandro Biondi 001; Daniel Casini; Giorgiomaria Cicero; Niccolò Borgioli; Giorgio C. Buttazzo; Gaetano Patti; Luca Leonardi; Lucia Lo Bello; Marco Solieri; Paolo Burgio; Ignacio Sanudo Olmedo; Angelo Ruocco; et al. (IEEE Access, 2021)

Front Matter - ECRTS 2021 Artifacts, Table of Contents, Artifact Evaluation Committee. - Alessandro Biondi 001; Angeliki Kritikakou (Dagstuhl Artifacts Ser., 2021)

Task Splitting and Load Balancing of Dynamic Real-Time Workloads for Semi-Partitioned EDF. - Daniel Casini; Alessandro Biondi 001; Giorgio Carlo Buttazzo (IEEE Trans. Computers, 2021)

Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs. - Biruk B. Seyoum; Marco Pagani; Alessandro Biondi 001; Sara Balleri; Giorgio C. Buttazzo (IEEE Trans. Computers, 2021)

Placement of Chains of Real-Time Tasks on Heterogeneous Platforms under EDF Scheduling. - Daniel Casini; Alessandro Biondi 001 (DSD, 2022)

Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC. - Gerlando Sciangula; Francesco Restuccia 002; Alessandro Biondi 001; Giorgio C. Buttazzo (DSD, 2022)

Response-Time Analysis for Self-Suspending Tasks Under EDF Scheduling. - Federico Aromolo; Alessandro Biondi 001; Geoffrey Nelissen (ECRTS, 2022)

PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms. - Gabriele Serra; Pietro Fara; Giorgiomaria Cicero; Francesco Restuccia 002; Alessandro Biondi 001 (RTAS, 2022)

Evaluating the Robustness of Semantic Segmentation for Autonomous Driving against Real-World Adversarial Patch Attacks. - Federico Nesti; Giulio Rossolini; Saasha Nair; Alessandro Biondi 001; Giorgio C. Buttazzo (WACV, 2022)

CARLA-GeAR: a Dataset Generator for a Systematic Evaluation of Adversarial Robustness of Vision Models. - Federico Nesti; Giulio Rossolini; Gianluca D'Amico; Alessandro Biondi 001; Giorgio C. Buttazzo (CoRR, 2022)

Response-Time Analysis for Self-Suspending Tasks Under EDF Scheduling (Artifact). - Federico Aromolo; Alessandro Biondi 001; Geoffrey Nelissen (Dagstuhl Artifacts Ser., 2022)

A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration. - Marco Pagani; Alessandro Biondi 001; Mauro Marinoni; Lorenzo Molinari; Giuseppe Lipari; Giorgio Carlo Buttazzo (Future Gener. Comput. Syst., 2022)

Partitioning real-time workloads on multi-core virtual machines. - Luca Abeni; Alessandro Biondi 001; Enrico Bini (J. Syst. Archit., 2022)

Optimized partitioning and priority assignment of real-time applications on heterogeneous platforms with hardware acceleration. - Daniel Casini; Paolo Pazzaglia; Alessandro Biondi 001; Marco Di Natale (J. Syst. Archit., 2022)

ARTe: Providing real-time multitasking to Arduino. - Francesco Restuccia 002; Marco Pagani; Agostino Mascitti; Michael Barrow; Mauro Marinoni; Alessandro Biondi 001; Giorgio C. Buttazzo; Ryan Kastner (J. Syst. Softw., 2022)

Profiling and controlling I/O-related memory contention in COTS heterogeneous platforms. - Matteo Zini; Giorgiomaria Cicero; Daniel Casini; Alessandro Biondi 001 (Softw. Pract. Exp., 2022)

An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems. - Niccolò Borgioli; Matteo Zini; Daniel Casini; Giorgiomaria Cicero; Alessandro Biondi 001; Giorgio C. Buttazzo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Robust-by-Design Classification via Unitary-Gradient Neural Networks. - Fabio Brau; Giulio Rossolini; Alessandro Biondi 001; Giorgio C. Buttazzo (AAAI, 2023)

Defending from Physically-Realizable Adversarial Attacks through Internal Over-Activation Analysis. - Giulio Rossolini; Federico Nesti; Fabio Brau; Alessandro Biondi 001; Giorgio C. Buttazzo (AAAI, 2023)

Real-Time Packet-Based Intrusion Detection on Edge Devices. - Niccolò Borgioli; Linh Thi Xuan Phan; Federico Aromolo; Alessandro Biondi 001; Giorgio C. Buttazzo (CPS-IoT Week Workshops, 2023)

Replication-Based Scheduling of Parallel Real-Time Tasks. - Federico Aromolo; Geoffrey Nelissen; Alessandro Biondi 001 (ECRTS, 2023)

Bounding the Data-Delivery Latency of DDS Messages in Real-Time Applications. - Gerlando Sciangula; Daniel Casini; Alessandro Biondi 001; Claudio Scordino; Marco Di Natale (ECRTS, 2023)

Virtualized DDS Communication for Multi-Domain Systems: Architecture and Performance Evaluation of Design Alternatives. - Andrea Stevanato; Alessandro Biondi 001; Alessandro Biasci; Bruno Morelli (RTAS, 2023)

Maximizing the Security Level of Real-Time Software While Preserving Temporal Constraints. - Sandro Di Leonardi; Federico Aromolo; Pietro Fara; Gabriele Serra; Daniel Casini; Alessandro Biondi 001; Giorgio C. Buttazzo (IEEE Access, 2023)

Optimizing Inter-Core Communications Under the LET Paradigm using DMA Engines. - Paolo Pazzaglia; Daniel Casini; Alessandro Biondi 001; Marco Di Natale (IEEE Trans. Computers, 2023)

Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs. - Francesco Restuccia 002; Marco Pagani; Alessandro Biondi 001; Mauro Marinoni; Giorgio C. Buttazzo (IEEE Trans. Computers, 2023)

Analyzing Arm's MPAM From the Perspective of Time Predictability. - Matteo Zini; Daniel Casini; Alessandro Biondi 001 (IEEE Trans. Computers, 2023)

Increasing the Confidence of Deep Neural Networks by Coverage Analysis. - Giulio Rossolini; Alessandro Biondi 001; Giorgio C. Buttazzo (IEEE Trans. Software Eng., 2023)

Detecting Adversarial Examples by Input Transformations, Defense Perturbations, and Voting. - Federico Nesti; Alessandro Biondi 001; Giorgio Carlo Buttazzo (IEEE Trans. Neural Networks Learn. Syst., 2023)

On the Minimal Adversarial Perturbation for Deep Neural Networks With Provable Estimation Error. - Fabio Brau; Giulio Rossolini; Alessandro Biondi 001; Giorgio C. Buttazzo (IEEE Trans. Pattern Anal. Mach. Intell., 2023)

Supporting logical execution time in multi-core POSIX systems. - Davide Bellassai; Alessandro Biondi 001; Alessandro Biasci; Bruno Morelli (J. Syst. Archit., 2023)

Supporting AI-powered real-time cyber-physical systems on heterogeneous platforms via hypervisor technology. - Edoardo Cittadini; Mauro Marinoni; Alessandro Biondi 001; Giorgiomaria Cicero; Giorgio C. Buttazzo (Real Time Syst., 2023)

AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs. - Thomas Benz; Alessandro Ottaviano; Robert Balas; Angelo Garofalo; Francesco Restuccia 002; Alessandro Biondi 001; Luca Benini (DATE, 2024)

End-to-End Latency Optimization of Thread Chains Under the DDS Publish/Subscribe Middleware. - Gerlando Sciangula; Daniel Casini; Alessandro Biondi 001; Claudio Scordino (DATE, 2024)

Optimizing Per-Core Priorities to Minimize End-To-End Latencies. - Francesco Paladino; Alessandro Biondi 001; Enrico Bini; Paolo Pazzaglia (ECRTS, 2024)

Attention-Based Real-Time Defenses for Physical Adversarial Attacks in Vision Applications. - Giulio Rossolini; Alessandro Biondi 001; Giorgio C. Buttazzo (ICCPS, 2024)

RT-Mimalloc: A New Look at Dynamic Memory Allocation for Real-Time Systems. - Raffaele Giannessi; Alessandro Biondi 001; Alessandro Biasci (RTAS, 2024)

In Search of Butterflies: Exceedance Analysis for Real-Time Systems under Transient Overload. - Matteo Zini; Filip Markovic 001; Daniel Casini; Alessandro Biondi 001; Björn B. Brandenburg (RTSS, 2024)

Edge-Only Universal Adversarial Attacks in Distributed Learning. - Giulio Rossolini; Tommaso Baldi; Alessandro Biondi 001; Giorgio C. Buttazzo (CoRR, 2024)

CARLA-GeAR: A Dataset Generator for a Systematic Evaluation of Adversarial Robustness of Deep Learning Vision Models. - Federico Nesti; Giulio Rossolini; Gianluca D'Amico; Alessandro Biondi 001; Giorgio C. Buttazzo (IEEE Trans. Intell. Transp. Syst., 2024)

Learning Memory-Contention Timing Models With Automated Platform Profiling. - Andrea Stevanato; Matteo Zini; Alessandro Biondi 001; Bruno Morelli; Alessandro Biasci (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

On the Real-World Adversarial Robustness of Real-Time Semantic Segmentation Models for Autonomous Driving. - Giulio Rossolini; Federico Nesti; Gianluca D'Amico; Saasha Nair; Alessandro Biondi 001; Giorgio C. Buttazzo (IEEE Trans. Neural Networks Learn. Syst., 2024)

Modeling the SL-LET Paradigm in AUTOSAR Adaptive. - Davide Bellassai; Gerlando Sciangula; Claudio Scordino; Daniel Casini; Alessandro Biondi 001 (DATE, 2025)

Enabling Containerisation of Distributed Applications with Real-Time Constraints. - Nasim Samimi; Luca Abeni; Daniel Casini; Mauro Marinoni; Twan Basten; Mitra Nasri; Marc Geilen; Alessandro Biondi 001 (ECRTS, 2025)

Integrating the Simplex Architecture to Enhance Safety in Deep Learning Autonomous Systems. - Niko Salamini; Federico Nesti; Mauro Marinoni; Giorgiomaria Cicero; Gabriele Serra; Alessandro Biondi 001; Giorgio C. Buttazzo (ICCPS, 2025)

A Design Flow to Securely Isolate FPGA Bus Transactions in Heterogeneous SoCs. - Niko Salamini; Sara Alonso Salazar; Gabriele Serra; Giorgiomaria Cicero; Pietro Fara; Federico Aromolo; Alessandro Biondi 001 (RTAS, 2025)

AP-LET: Enabling deterministic Pub/Sub communication in AUTOSAR Adaptive. - Davide Bellassai; Claudio Scordino; Daniel Casini; Alessandro Biondi 001 (J. Syst. Archit., 2025)

Hazardous Behavior Analysis for Complex Pre-Existing Software in Safety-Critical Context: Approach and Application to the Linux Dynamic Memory Allocator. - Raffaele Giannessi; Fabrizio Tronci; Alessandro Biondi 001 (IEEE Trans. Dependable Secur. Comput., 2025)

Loss Landscape Analysis for Reliable Quantized ML Models for Scientific Sensing. - Tommaso Baldi; Javier Campos; Olivia Weng; Caleb Geniesse; Nhan Tran; Ryan Kastner; Alessandro Biondi 001 (CoRR, 2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. - Angelo Garofalo; Alessandro Ottaviano; Matteo Perotti; Thomas Benz; Yvan Tortorella; Robert Balas; Michael Rogenmoser; Chi Zhang; Luca Bertaccini; Nils Wistoff; Maicol Ciani; Cyril Koenig; et al. (CoRR, 2025)

Benchmarking the Spatial Robustness of DNNs via Natural and Adversarial Localized Corruptions. - Giulia Marchiori Pietrosanti; Giulio Rossolini; Alessandro Biondi 001; Giorgio C. Buttazzo (CoRR, 2025)

Exploiting Inaccurate Branch History in Side-Channel Attacks. - Yuhui Zhu; Alessandro Biondi 001 (CoRR, 2025)

Exploiting Edge Features for Transferable Adversarial Attacks in Distributed Machine Learning. - Giulio Rossolini; Fabio Brau; Alessandro Biondi 001; Battista Biggio; Giorgio C. Buttazzo (CoRR, 2025)

AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems. - Thomas Benz; Alessandro Ottaviano; Chaoqun Liang; Robert Balas; Angelo Garofalo; Francesco Restuccia 002; Alessandro Biondi 001; Davide Rossi; Luca Benini (IEEE Trans. Computers, 2025)