Design space exploration for field programmable compressor trees. - Seyed-Hosein Attarzadeh-Niaki; Alessandro Cevrero; Philip Brisk; Chrysostomos Nicopoulos; Frank K. Gürkaynak; Yusuf Leblebici; Paolo Ienne (CASES, 2008)

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Philip Brisk; Frank K. Gürkaynak; Yusuf Leblebici; Paolo Ienne (FPGA, 2008)

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. - Francesco Regazzoni 001; Alessandro Cevrero; François-Xavier Standaert; Stéphane Badel; Theo Kluter; Philip Brisk; Yusuf Leblebici; Paolo Ienne (CHES, 2009)

FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. - Arun Paidimarri; Alessandro Cevrero; Philip Brisk; Paolo Ienne (FCCM, 2009)

3D configuration caching for 2D FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Philip Brisk; Yusuf Leblebici; Paolo Ienne; Maurizio Skerlj (FPGA, 2009)

Using 3D integration technology to realize multi-context FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Maurizio Skerlj; Philip Brisk; Yusuf Leblebici; Paolo Ienne (FPL, 2009)

A flexible DSP block to enhance FPGA arithmetic performance. - Hadi Parandeh-Afshar; Alessandro Cevrero; Panagiotis Athanasopoulos; Philip Brisk; Yusuf Leblebici; Paolo Ienne (FPT, 2009)

Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. - Jani Boutellier; Alessandro Cevrero; Philip Brisk; Paolo Ienne (SiPS, 2009)

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Seyed-Hosein Attarzadeh-Niaki; Chrysostomos Nicopoulos; Frank K. Gürkaynak; Philip Brisk; Yusuf Leblebici; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2009)

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs. - Fengda Sun; Alessandro Cevrero; Panagiotis Athanasopoulos; Yusuf Leblebici (VLSI-SoC, 2010)

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. - Alessandro Cevrero; Francesco Regazzoni 001; Micheal Schwander; Stéphane Badel; Paolo Ienne; Yusuf Leblebici (DAC, 2011)

Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders. - Christoph Roth; Alessandro Cevrero; Christoph Studer; Yusuf Leblebici; Andreas Burg 001 (ISCAS, 2011)

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology. - Giulia Beanato; Paolo Giovannini; Alessandro Cevrero; Panagiotis Athanasopoulos; Michael Zervas; Yuksel Temiz; Yusuf Leblebici (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Fast and accurate BER estimation methodology for I/O links based on extreme value theory. - Alessandro Cevrero; Nestor E. Evmorfopoulos; Charalampos Antoniadis; Paolo Ienne; Yusuf Leblebici; Andreas Burg 001; Georgios I. Stamoulis (DATE, 2013)

3D-MMC: a modular 3D multi-core architecture with efficient resource pooling. - Tiansheng Zhang; Alessandro Cevrero; Giulia Beanato; Panagiotis Athanasopoulos; Ayse K. Coskun; Yusuf Leblebici (DATE, 2013)

A parallelized layered QC-LDPC decoder for IEEE 802.11ad. - Alexios Balatsoukas-Stimming; Nicholas Preyss; Alessandro Cevrero; Andreas Burg 001; Christoph Roth (NEWCAS, 2013)

3D serial TSV link for low-power chip-to-chip communication. - Giulia Beanato; Alessandro Cevrero; Giovanni De Micheli; Yusuf Leblebici (ICICDT, 2014)

10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. - Pier Andrea Francese; Thomas Toifl; Matthias Braendli; Christian Menolfi; Marcel A. Kossel; Thomas Morf; Lukas Kull; Toke Meyer Andersen; Hazar Yueksel; Alessandro Cevrero; Danny Luu (ISSCC, 2015)

A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. - Alessandro Cevrero; Cosimo Aprile; Pier Andrea Francese; Urs Bapst; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Lukas Kull; Hazar Yueksel; Ilter Oezkaya; Yusuf Leblebici; et al. (VLSIC, 2015)

Design considerations for 50G+ backplane links. - Thomas Toifl; Matthias Braendli; Alessandro Cevrero; Pier Andrea Francese; Marcel A. Kossel; Lukas Kull; Danny Luu; Christian Menolfi; Thomas Morf; Ilter Özkaya; Hazar Yueksel (ESSCIRC, 2016)

23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path. - Pier Andrea Francese; Matthias Braendli; Christian Menolfi; Marcel A. Kossel; Thomas Morf; Lukas Kull; Alessandro Cevrero; Hazar Yueksel; Ilter Oezkaya; Danny Luu; Thomas Toifl (ISSCC, 2016)

Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors. - Giulia Beanato; Alessandro Cevrero; Giovanni De Micheli; Yusuf Leblebici (Microelectron. J., 2016)

Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs. - Giulia Beanato; Kiarash Gharibdoust; Alessandro Cevrero; Giovanni De Micheli; Yusuf Leblebici (Microelectron. J., 2016)

DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology. - Marcel A. Kossel; Christian Menolfi; Pier Andrea Francese; Lukas Kull; Thomas Morf; Thomas Toifl; Matthias Braendli; Alessandro Cevrero; Danny Luu; Ilter Özkaya; Hazar Yueksel (ESSCIRC, 2017)

Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET. - Danny Luu; Lukas Kull; Thomas Toifl; Christian Menolfi; Matthias Braendli; Pier Andrea Francese; Thomas Morf; Marcel A. Kossel; Hazar Yueksel; Alessandro Cevrero; Ilter Özkaya; Qiuting Huang (ESSCIRC, 2017)

Adaptive high-speed and ultra-low power optical interconnect for data center communications. - Ronny Henker; Thomas Toifl; Alessandro Cevrero; Ilter Oezkaya; Michael Georgiades; Mahdi M. Khafaji; Jan Plíva; Frank Ellinger (ICTON, 2017)

29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. - Alessandro Cevrero; Ilter Özkaya; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; Benjamin G. Lee; et al. (ISSCC, 2017)

28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. - Lukas Kull; Danny Luu; Christian Menolfi; Matthias Braendli; Pier Andrea Francese; Thomas Morf; Marcel A. Kossel; Hazar Yueksel; Alessandro Cevrero; Ilter Özkaya; Thomas Toifl (ISSCC, 2017)

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. - Ilter Özkaya; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Christian W. Baks; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; et al. (IEEE J. Solid State Circuits, 2017)

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Thomas Toifl; et al. (ISCAS, 2018)

A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET. - Lukas Kull; Danny Luu; Christian Menolfi; Matthias Braendli; Pier Andrea Francese; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Thomas Toifl (ISSCC, 2018)

A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS. - Christian Menolfi; Matthias Braendli; Pier Andrea Francese; Thomas Morf; Alessandro Cevrero; Marcel A. Kossel; Lukas Kull; Danny Luu; Ilter Özkaya; Thomas Toifl (ISSCC, 2018)

A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. - Ilter Özkaya; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Thomas Morf; Daniel M. Kuchta; Lukas Kull; Marcel A. Kossel; Danny Luu; Mounir Meghelli; Yusuf Leblebici; et al. (ISSCC, 2018)

4×40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS. - Alessandro Cevrero; Ilter Özkaya; Thomas Morf; Thomas Toifl; M. Seifried; Frank Ellinger; Mohammad Mahdi Khafaji; Jan Plíva; Ronny Henker; Nikolay N. Ledentsov; J.-R. Kropp; V. A. Shchukin; et al. (OFC, 2018)

A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE. - Pier Andrea Francese; Alessandro Cevrero; Ilter Özkaya; Matthias Brändli; Christian Menolfi; Thomas Morf; Marcel A. Kossel; Lukas Kull; Danny Luu; Thomas Toifl (VLSI Circuits, 2018)

A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration. - Lukas Kull; Danny Luu; Christian Menolfi; Thomas Morf; Pier Andrea Francese; Matthias Braendli; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Thomas Toifl (VLSI Circuits, 2018)

A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS. - Thomas Toifl; Christian Menolfi; Matthias Brändli; Alessandro Cevrero; Pier Andrea Francese; Marcel A. Kossel; Lukas Kull; Danny Luu; Thomas Morf; Ilter Özkaya (VLSI Circuits, 2018)

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. - Cosimo Aprile; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Lukas Kull; Ilter Oezkaya; Yusuf Leblebici; Volkan Cevher; Thomas Toifl (IEEE J. Solid State Circuits, 2018)

A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET. - Lukas Kull; Danny Luu; Christian Menolfi; Matthias Brändli; Pier Andrea Francese; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Thomas Toifl (IEEE J. Solid State Circuits, 2018)

A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET. - Danny Luu; Lukas Kull; Thomas Toifl; Christian Menolfi; Matthias Braendli; Pier Andrea Francese; Thomas Morf; Marcel A. Kossel; Hazar Yueksel; Alessandro Cevrero; Ilter Özkaya; Qiuting Huang (IEEE J. Solid State Circuits, 2018)

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. - Ilter Özkaya; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Christian W. Baks; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; et al. (IEEE J. Solid State Circuits, 2018)

A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. - Jonathan E. Proesel; Zeynep Toprak Deniz; Alessandro Cevrero; Ilter Özkaya; Seongwon Kim; Daniel M. Kuchta; Sungjae Lee 005; Sergey V. Rylov; Herschel A. Ainspan; Timothy O. Dickson; John F. Bulzacchelli; Mounir Meghelli (IEEE J. Solid State Circuits, 2018)

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; et al. (A-SSCC, 2019)

A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET. - Alessandro Cevrero; Ilter Özkaya; Pier Andrea Francese; Matthias Brändli; Christian Menolfi; Thomas Morf; Marcel A. Kossel; Lukas Kull; Danny Luu; Martino Dazzi; Thomas Toifl (ISSCC, 2019)

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; et al. (ISSCC, 2019)

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. - Gain Kim; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Andreas Burg 001; Thomas Toifl; Yusuf Leblebici; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; et al. (IEEE J. Solid State Circuits, 2020)