A Single-Inductor Two-Step-Mixing Injection-Locked Frequency Divider by Four with Concurrent Tail-Injection. - Alessandro Garghetti; Andrea L. Lacaita; Salvatore Levantino (ICECS, 2018)

A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique. - Alessandro Garghetti; Andrea L. Lacaita; Salvatore Levantino (ISCAS, 2018)

A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS. - Luigi Grimaldi; Luca Bertulessi; Saleh Karman; Dmytro Cherniak; Alessandro Garghetti; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (ISSCC, 2019)

A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. - Luca Bertulessi; Saleh Karman; Dmytro Cherniak; Alessandro Garghetti; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2019)

A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking. - Alessandro Garghetti; Andrea L. Lacaita; Salvatore Levantino (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS. - Alessandro Garghetti; Andrea Leonardo Lacaita; David Seebacher; Matteo Bassi; Salvatore Levantino (CICC, 2021)

Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology. - Alessandro Garghetti; Andrea L. Lacaita; David Seebacher; Matteo Bassi; Salvatore Levantino (IEEE J. Solid State Circuits, 2022)