Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training. - Angelo Garofalo; Matteo Perotti; Luca Valente; Yvan Tortorella; Alessandro Nadalini; Luca Benini; Davide Rossi; Francesco Conti 001 (ESSCIRC, 2022)

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. - Luca Valente; Asif Veeran; Mattia Sinigaglia; Yvan Tortorella; Alessandro Nadalini; Nils Wistoff; Bruno Sá; Angelo Garofalo; Rafail Psiakis; M. Tolba; Ari Kulmala; Nimisha Limaye; et al. (HCS, 2023)

A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks. - Alessandro Nadalini; Georg Rutishauser; Alessio Burrello; Nazareno Bruschi; Angelo Garofalo; Luca Benini; Francesco Conti 001; Davide Rossi (ISVLSI, 2023)

DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training. - Angelo Garofalo; Yvan Tortorella; Matteo Perotti; Luca Valente; Alessandro Nadalini; Luca Benini; Davide Rossi; Francesco Conti 001 (CoRR, 2023)

A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation. - Luca Valente; Alessandro Nadalini; Asif Hussain Chiralil Veeran; Mattia Sinigaglia; Bruno Sá; Nils Wistoff; Yvan Tortorella; Simone Benatti; Rafail Psiakis; Ari Kulmala; Baker Mohammad; Sandro Pinto 001; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators. - Victor Isachi; Alessandro Nadalini; Riccardo Fiorani Gallotta; Angelo Garofalo; Francesco Conti 001; Davide Rossi (CF, 2025)

FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators. - Chi Zhang; Luca Colagrande; Renzo Andri; Thomas Benz; Gamze Islamoglu; Alessandro Nadalini; Francesco Conti 001; Yawei Li 001; Luca Benini (ISVLSI, 2025)