A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. - Alessio Santiccioli; Mario Mercandelli; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (CICC, 2019)

A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power. - Alessio Santiccioli; Mario Mercandelli; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2019)

Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops. - Alessio Santiccioli; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Angelo Parisi; Luca Bertulessi; Dmytro Cherniak; Andrea Leonardo Lacaita; Carlo Samori; Salvatore Levantino (ISSCC, 2020)

17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. - Alessio Santiccioli; Mario Mercandelli; Luca Bertulessi; Angelo Parisi; Dmytro Cherniak; Andrea Leonardo Lacaita; Carlo Samori; Salvatore Levantino (ISSCC, 2020)

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. - Alessio Santiccioli; Mario Mercandelli; Luca Bertulessi; Angelo Parisi; Dmytro Cherniak; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2020)

High-efficiency inductorless frequency synthesis. - Alessio Santiccioli (2020)

A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Simone Mattia Dartizio; Abanob Shehata; Francesco Tesolin; Saleh Karman; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Andrea Leonardo Lacaita; Michael Peter Kennedy; et al. (ISSCC, 2021)

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. - Alessio Santiccioli; Mario Mercandelli; Simone Mattia Dartizio; Francesco Tesolin; Saleh Karman; Abanob Shehata; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Dmytro Cherniak; Andrea L. Lacaita; et al. (ISSCC, 2021)

A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs. - Luca Avallone; Mario Mercandelli; Alessio Santiccioli; Michael Peter Kennedy; Salvatore Levantino; Carlo Samori (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Andrea Bevilacqua; Luca Bertulessi; Dmytro Cherniak; Carlo Samori; Andrea L. Lacaita; et al. (CICC, 2022)

A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea Leonardo Lacaita; et al. (ISSCC, 2022)

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2022)

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. - Simone Mattia Dartizio; Francesco Tesolin; Mario Mercandelli; Alessio Santiccioli; Abanob Shehata; Saleh Karman; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Andrea L. Lacaita; Michael Peter Kennedy; et al. (IEEE J. Solid State Circuits, 2022)

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Angelo Parisi; Luca Bertulessi; Dmytro Cherniak; Andrea L. Lacaita; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2022)

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2023)

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays. - Francesco Tesolin; Simone Mattia Dartizio; Francesco Buccoleri; Alessio Santiccioli; Luca Bertulessi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2023)